Patent
1976-08-04
1978-04-25
Springborn, Harvey E.
179 15BV, H04J 304
Patent
active
040864367
ABSTRACT:
Each of first N flip-flop stages, where N is an integer greater than one, has steered thereto an appropriate one of N bits of the data to be transmitted by a transmit write counter and a first N stage decoder under control of a transmit write clock. A transmit read counter under control of a transmit read clock steers the stored bits to a transmit data bus by means of a first multiplexer and first logic circuitry under control of a transmit read counter and a transmit channel timing signal. Each of second N flip-flop stages has steered thereto an appropriate one of N bits of received data by a receive write counter and a second N stage decoder under control of a receive write clock. A receive read counter under control of a receive read clock steers the stored bits to a receive data bus by means of a second multiplexer and second logic circuitry under control of the receive read counter.
REFERENCES:
patent: 3569631 (1971-03-01), Johannes et al.
patent: 3663760 (1972-05-01), De Witt
patent: 3868481 (1975-02-01), Patrusky et al.
patent: 3873773 (1975-03-01), Guy, Jr.
Clark James Monroe
Cohen Stuart Barry
Magnus Arthur Howard
Hill Alfred C.
International Telephone and Telegraph Corporation
O'Halloran John T.
Springborn Harvey E.
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