Transmission system with random error and burst error correction

Details Transmission system with random error and burst error correction Transmission system with random error and burst error correction

1992-10-27

1994-12-27

Beausoliel, Jr.

Excavating

371 391, 371 44, 371 45, G06F 1110

Patent

active

053772083

ABSTRACT:
The invention relates to a transmission system comprising a transmitter (100) which includes a coder for coding an information signal (11) into a digital signal (11, 12) constituted by the information signal (11) and a redundancy signal (12), the redundancy signal (12) being generated by way of a cyclic code from the information signal (11 ), and comprising a receiver (101) which includes a decoder with a storage unit (2) for storing the information signal (11) and with an error correction means which has an optionally feedback shift register (3) for processing the digital signal (11, 12). The transmission system is to make both the correction of burst errors as well as the correction of random errors possible in a single error correction means. There is proposed that the error correction means of the decoder comprises a burst error detection means (4) for producing a first error information signal (B) from predeterminable storage contents (S.sub.0 . . . S.sub.11) of the shift register (3) and a random error detection means (5) for producing a second error information signal (E) from the aggregate storage contents (S.sub.0 . . . S.sub.11) of the shift register (3), and that a control means (8) is provided for evaluating the first error information signal (B) and second error information signal (E) and combining means (E1) are provided for combining the storage contents (S.sub.0 . . . S.sub.17) of the shift register (3) with the storage contents of the storage unit (2). The transmission system may be used for example, in video communication systems.

REFERENCES:
patent: 3775746 (1973-11-01), Boudreau et al.
patent: 3831143 (1974-08-01), Trafton
patent: 4592054 (1986-05-01), Namekawa et al.
patent: 4951284 (1990-08-01), Abdel-Ghaffar et al.
patent: 5179560 (1993-01-01), Yamagishi et al.
Microprocessors and Microsystems Bd. 14, Nr. 4, May 1990, London, GB pp. 256-262 by Almaini et al "ASIC implementation of a programmable error-trapping decoder for binary codes of length 15".
S. Lin et al., "Error Control Coding Fundamentals and Application", pp. 125-131 to 259-282.

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