Electrical computers and digital processing systems: multicomput – Computer-to-computer protocol implementing – Computer-to-computer data framing
Reexamination Certificate
2000-06-30
2004-06-08
Meky, Moustafa M. (Department: 2157)
Electrical computers and digital processing systems: multicomput
Computer-to-computer protocol implementing
Computer-to-computer data framing
C709S224000, C370S231000
Reexamination Certificate
active
06748444
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a transmission system of short time lag (meaning a reduced small time lag) where a task is started, in the state that a delay time period, a timer interrupt process time period and the like are predicted, based on a periodic interrupt as a trigger, and a packet transmission is started within a limited time period (requested time period for processing).
2. Description of the Related Art
FIG. 19
shows a configuration of a task wait time controller used in a conventional computer system, disclosed in Unexamined Japanese Patent Publication HEI 7-152588. In
FIG. 19
, there provided a system bus
201
, a CPU (Central Calculation Processing Unit)
202
for executing various information processes, a ROM (Read Only Memory)
203
for memorizing fixed data of operating system (OS), application program etc, a RAM (Random Access Memory)
204
for memorizing various variable data as a main memory, an input/output port
205
for receiving and transmitting data from/to an external device, a system timer
206
, and a real timer
207
.
In the task wait time controller for the conventional computer system as shown in
FIG. 19
, two timers are used for measuring a specified wait time period of task execution request. One is the system timer
206
which is usually used for outputting a periodic interrupt request at a regular cycle and the other is the real timer
207
which measures a remainder time calculated by subtracting an odd time period from a wait time period and dividing the subtracted time period by the regular cycle. By dint of using the two timers, the CPU does not need to execute a useless interrupt process and each task is started at an accurate timing designated by each specified wait time.
The task wait time controller set forth above has a problem that a delay time period of interrupt process in the H/W is not taken into consideration. The real timer wait queue setting process of
FIG. 20
shows the case that a specified wait time is set as a set value of the real timer
207
at a step
211
when the specified wait time is larger than a regular cycle. In this case, there is a problem that a delay time period occurred during the steps from
211
up to
221
where the real timer
207
is actually started is not taken into the consideration. Therefore, it is difficult to accurately start up a task at the timing specified by the specified wait time of task execution request.
In the task execution requests, some are requesting to execute tasks when the specified time period has passed since the current time, and others are requesting to execute tasks within a specified limited time period. For instance, sensor data is transferred to a server through an Ethernet at a specified cycle, in the electric power substation. In this case, it is requested to complete processes up to starting the data transmission to the Ethernet within 225±25 &mgr;s based on an interrupt generated at a specific period as a reference. For dealing with this kind of request, it is not enough to execute a task after the specified time period having passed since the current time, as has been done in the conventional system. This is a problem of the conventional one.
One of the objects of the preferred embodiment of the present invention is to provide a transmission system of short time lag in which a packet transmission can be started within a limited time period based on a periodic interrupt as a trigger in the state that a delay time period, such as the time period of the H/W process responsive to an interrupt, the S/W process needed for starting up a timer, and a time period from the task starting to the packet transmission beginning are predicted, and in the state that a timer interrupt generation time for starting up the task is set based on the predicted time period. Another object is to lessen a time lag of the time period spent from the periodic interrupt to the packet transmission starting.
SUMMARY OF THE INVENTION
According to one aspect of a transmission system of the present invention, in which a packet is formed and transmitted within a specific time period, the transmission system comprises:
a periodic interrupt generating part for generating a periodic interrupt at intervals longer than the specific time period;
a relative time timer in which a specific timer set value is set, for generating an interrupt by measuring a specific elapse time based on the specific timer set value;
a control information memorizing part for memorizing control information used for calculating the specific elapse time measured by the relative time timer;
a set value calculating part for calculating the specific timer set value to be measured by the relative time timer, by using the control information memorized in the control information memorizing part;
a packet forming part, which is started when the periodic interrupt by the periodic interrupt generating part occurs, for setting the specific timer set value calculated by the set value calculating part in the relative time timer and forming a packet; and
a transmission requesting part, which is started when the interrupt by the relative time timer occurs, for transmitting the packet formed by the packet forming part.
According to one aspect of a transmission method for the transmission system of the present invention, in which a packet is formed and transmitted within a specific time period, the transmission method comprises:
generating a periodic interrupt at intervals longer than the specific time period;
generating an interrupt by measuring a specific elapse time based on a specific timer set value;
memorizing control information used for calculating the specific elapse time;
calculating the specific timer set value to be measured by a relative time timer, by using the control information;
when the periodic interrupt occurs, setting the specific timer set value in the relative time timer and forming a packet; and
when the interrupt occurs, transmitting the packet.
The above-mentioned and other objects, features, and advantages of the present invention will be made more apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 4894819 (1990-01-01), Kondo et al.
patent: 5090011 (1992-02-01), Fukuta et al.
patent: 5465354 (1995-11-01), Hirosawa et al.
patent: 5862338 (1999-01-01), Walker et al.
patent: 6067563 (2000-05-01), Thomas et al.
patent: 6094434 (2000-07-01), Kotzur et al.
patent: 6483845 (2002-11-01), Takeda et al.
patent: A5265775 (1993-10-01), None
patent: A667899 (1994-03-01), None
patent: A7152588 (1995-06-01), None
Birch & Stewart Kolasch & Birch, LLP
Meky Moustafa M.
Mitsubishi Denki & Kabushiki Kaisha
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