Multiplex communications – Wide area network – Packet switching
Patent
1993-11-05
1994-11-01
Hsu, Alpus H.
Multiplex communications
Wide area network
Packet switching
370108, 375112, 375118, 369 60, 36518905, H04J 306, H04L 704
Patent
active
053612639
ABSTRACT:
A transmission system for the synchronous digital hierarchy, comprising an adaptation circuit for compensating for phase variations of an STM-N signal. The adaptation circuit (8) comprises a buffer (17, 33), a write address generator (16, 35), a read address generator (18, 44), a justification decision circuit (24, 43) and an output circuit (19, 45), for inserting justification locations for at least one container of the STM-N signal. The buffer is provided for writing and reading the container data. The write address generator is provided for generating write addresses for the data to be written and the read address generator is provided for generating read addresses for the data to be read out. The justification decision circuit is used for forming the mean value of the differences of the addresses of the read and write address generators over a specific period of time and for forming a justification signal as a function of the mean value. The output circuit is provided for generating negative or positive justification locations in the container as a function of the justification signal and for generating an output signal on the basis of the data stored in the buffer.
REFERENCES:
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CCITT Recommendations G707, G708, G709, and G783.
M. Robeldo et al., "Jitter bei der Ubertragung plesiochroner Signale in der SDH" PKI Techn. Mitt. Mar. 1989, pp. 31-38.
Hsu Alpus H.
Treacy David R.
U.S. Philips Corporation
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