Transmission system for the synchronous digital hierarchy

Multiplex communications – Wide area network – Packet switching

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Details

370108, 375112, 375118, 369 60, 36518905, H04J 306, H04L 704

Patent

active

053434765

ABSTRACT:
A digital transmission system having at least one adaptation circuit for compensating for phase variations of a STM-N signal. For inserting justification locations for at least one container of the STM-N signal, the adaptation circuit (8) includes a buffer (17, 51), a write address generator (16, 53), a read address generator (18, 61) a justification decision circuit (24, 60) and an output circuit (19, 62). The buffer stores container data in which justification locations may be inserted. The write address generator provides write addresses for data to be written in the buffer, and the read address generator provides read addresses in the buffer. In one embodiment differences between the read and write address values are combined with justification information which has been low pass filtered. In another embodiment these differences are low pass filtered and used for forming the justification decision signal. The output circuit inserts positive or negative justification locations in data read from the buffer to form the container.

REFERENCES:
patent: 4791652 (1988-12-01), McEachern et al.
patent: 4811340 (1989-03-01), McEachern et al.
patent: 4891788 (1990-01-01), Kreifels
patent: 4928275 (1990-05-01), Moore et al.
patent: 5123010 (1992-06-01), Pospischil
patent: 5131013 (1992-07-01), Choi
patent: 5157655 (1992-10-01), Hamlin, Jr et al.
patent: 5168494 (1992-12-01), Mueller
"Jitter bei der Ubertragung plesiochroner Signale in der SDH", by Miguel Robledo and Ralph Urbansky, PKI Techn. Mitt. Mar. 1989, pp. 31-38.
CCIT Recommendation G707, G708, G709, pp. 107-173.

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