Transmission of a clock signal over an asynchronous data channel

Details Transmission of a clock signal over an asynchronous data channel Transmission of a clock signal over an asynchronous data channel

1992-04-10

1994-10-04

Chin, Stephen

Pulse or digital communications

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Direct sequence

375110, 370102, H04L 700, H04L 2536

Patent

active

053533135

ABSTRACT:
An input clock signal associated with an input data signal is divided by a predetermined integer N, to form a sub-rate clock signal. The sub-rate clock signal is sampled and transmitted along with the input data over an asynchronous data channel. At the receiver, the resulting sub-rate clock signal is received and coupled to a phase lock loop which generates a recovered clock signal of the same frequency and substantially in phase with the input clock signal.

REFERENCES:
patent: 4718074 (1988-01-01), Mannas et al.
patent: 4731646 (1988-03-01), Kliem
patent: 5014271 (1991-05-01), Fujimoto et al.

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