Transmission logic parity circuit

Details Transmission logic parity circuit Transmission logic parity circuit

1981-12-21

1984-05-29

Atkinson, Charles E.

Excavating

307572, G06F 1110, H04L 110

Patent

active

044519222

ABSTRACT:
An FET transmission logic parity circuit is disclosed which determines the odd or even status of register bits using zero DC current transmission logic. The circuit has a first two FET devices which propagate the state of the preceding odd or even nodes and the corresponding register bit is logically a zero. A second pair of FET devices switch the state of the odd or even nodes when the corresponding register bit is logically a one. In this manner, the output nodes are statically conditioned to either a first potential or a second potential, depending upon the register bit states and no DC current flows between the first and second potential.

REFERENCES:
patent: 3846751 (1974-11-01), Prieto
patent: 4006365 (1977-02-01), Marzin et al.
patent: 4049974 (1977-09-01), Boone et al.

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