Electricity: measuring and testing – Electrostatic field
Reexamination Certificate
2001-04-06
2003-05-27
Oda, Christine (Department: 2858)
Electricity: measuring and testing
Electrostatic field
C324S678000, C324S765010
Reexamination Certificate
active
06570388
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a method for measuring electrostatic discharge voltages by using transmission line pulse method, and in particular to a method which introduces a parasitic series resistance for solving electrostatic discharge voltages by using transmission line pulse method and least square error solution method.
2. Description of the Prior Art
In integrated circuit manufacturing and handling environments, there are three principal sources of electrostatic charging and discharging. The first and most common source to date of electrostatic discharge (ESD) is that due to human handling. The second source of ESD is that which takes place in automated test and handling systems. The equipment can accumulate static charge due to improper grounding, which is then transmitted through the IC when it is picked up for placement in the test socket or carrier. The third possibility is that the IC itself is charged during transport or because of contact with a highly charged surface or material. The IC remains charged until it comes into contact with a grounded surface such as a large metal plate or a test socket. It is then discharged through its pins and the large currents in the internal interconnect can result in high voltages inside the device. These voltages can cause damage to the very thin dielectrics and insulators present in the IC.
The three ESD mechanisms are known as (1) human body model (HBM), (2) machine model (MM), and (3) charged device model (CDM).
Failure modes for the HBM and the MM test methods are typically found in the diffusion regions of the protection circuits. However, CDM failures are usually gate oxide damage either at the pad, or in some cases internally in the circuit. The most common location for gate oxide damage is in the pMOS transistor of the input buffer. The HBM test method is the most popular standard method, and an equivalent ESD circuit for modeling HBM is shown in
FIG. 1
, and the discharge waveform of HBM is then shown in FIG.
2
.
The high current, short duration pulse can be easily reproduced using a charged transmission line. The advantage of the transmission line pulse (TLP) tester is that a constant current pulse is generated which enables the behavior of the protection structure under current conditions to be studied. The double exponential and oscillating pulses of standard ESD testers make it difficult to determine how the protection structure operates. Hence, the TLP tester has become popular with many ESD protection circuit designers and researchers into protection circuit operation and physics.
The TLP tester configuration has the advantage that it is easily designed to avoid sensitivity to internal parasitic elements. Hence, we obtain reproducible testing which can be correlated to HBM or MM type discharges.
The relationship between TLP method and HBM can be described as the following equation:
V
ESD-HBM
=I
t2
×R
HBM
Eq.(1)
wherein the V
ESD-HBM
is the electrostatic discharge voltage measured by the human body method, I
t2
is the second breakdown trigger current, and the R
HBM
is the resistance of a resistor used in HBM. R
HBM
is set equal to 1500 ohm in the TLP method. After measuring the second breakdown trigger current by TLP method, we will be able to calculate an equivalent electrostatic discharge voltage which is assumed to be equal to that measured by HBM.
In the Eq. 1, the R
HBM
is just a human body equivalent resistance, and the resistance of devices and leads is neglected. However, we found that the resistance of devices and leads is significant; thus we introduce the parasitic series resistance, Rs, to modify the Eq. 1.
SUMMARY OF THE INVENTION
It is an object of the invention to introduce a parasitic series resistance to modify the relationship between the transmission line pulse method and human body model.
It is another object of the invention to solve the parasitic series resistance and electrostatic discharge voltages.
According to the foregoing objects, the present invention introduces a parasitic series resistance into the Eq. 1, and then the equation become
electrostatic discharge voltage=electrostatic discharge current×(the human body equivalent resistance+parasitic series resistance)
In present invention, electrostatic discharge voltages and parasitic series resistances can be obtained by using the least square error solution method.
Firstly, the second breakdown trigger current I
t2
was measured by transmission line pulse method, and the electrostatic discharge voltage V
ESD-HBM
was measured by human body model test method. Then, the sum of square S=&Sgr;[the electrostatic discharge voltage measured by human body model test method V
ESD-HBM
−the second breakdown trigger current measured by transmission line pulse method I
t2
×(the human body equivalent resistance R
HBM
+parasitic series resistance Rs)]
2
∘ In order to get a optimal value of Rs, the sum of square is minimized. Then we can apply the value of parasitic serial resistance into Eq.2 to calculate the human body equivalent electrostatic discharge voltage of TLP method (V
ESD-TLP
).
Compare the human body equivalent electrostatic discharge voltage obtained from the TLP method with the electrostatic discharge voltage measured by HBM test method, we can find that the equation provided in this invention is better than that provided in prior art.
REFERENCES:
patent: 5804977 (1998-09-01), Consiglio
patent: 6147538 (2000-11-01), Andresen et al.
patent: 6429674 (2002-08-01), Barth et al.
Lee Ming-Tsan
Liu Chuan-Hsi
Benson Walter
Oda Christine
United Microeletronics Corp.
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