Transmission gate multiplexer (TGM) logic circuits and multiplie

Details Transmission gate multiplexer (TGM) logic circuits and multiplie Transmission gate multiplexer (TGM) logic circuits and multiplie

1990-04-16

1991-08-13

Shaw, Dale M.

Boots, shoes, and leggings

G06F 752

Patent

active

050401394

ABSTRACT:
Transmission gate multiplexer circuits (FIG. 5) are used to form Booth select logic (FIG. 12), Booth recode multiplexer logic (FIG. 11), constant K-bit logic (FIG. 13) and reduced sign bit logic (FIG. 14). In these circuits, input variables are selectively applied both to multiplexer input terminals and to multiplexer select terminals, to achieve the desired logic functions with minimum delay.

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H. Hnatek, User's Guidebook to Digital CMOS Circuits, (McGraw-Hill 1981) pp. 34-41.
R. R. Shively et al., "Cascading Transmission Gates to Enhance Multiplier Performance,"IEEE Transactions on Computers, vol. C-33, No. 7, Jul., 1984.
K. Yano et al., "A 3.8 ns 16.times.16 Multiplier Using Complementary Pass Transistor Logic", IEEE 1989 Custom Integrated Circuits Conference.

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