Boots – shoes – and leggings
Patent
1990-04-16
1993-04-06
Trans, Vincent N.
Boots, shoes, and leggings
364488, 364786, 307448, 307576, G06F 748, H03K 17687
Patent
active
052009076
ABSTRACT:
A method of designing a logic circuit for implementing a predetermined boolean function defines a binary tree structure formed of transmission gate multiplexer (TGM) circuits. The TGM tree structure includes one binary stage for each input variable. A resulting logic circuit design is reduced by one or more stages to improve performance by employing selected boolean functions of the most significant bits of the input variables as input signals to a reduced tree structure. The method is applicable circuit design in all MOS-type technologies including NMOS, PMOS, CMOS, BiMOS, FET and the like.
REFERENCES:
patent: 3783307 (1974-01-01), Breuer
patent: 4363107 (1982-12-01), Ohhashi et al.
patent: 4536855 (1985-08-01), Morton
patent: 4566064 (1986-01-01), Whitaker
patent: 4710649 (1987-12-01), Lewis
patent: 4736119 (1988-04-01), Chen et al.
patent: 4815003 (1989-03-01), Putatunda et al.
patent: 5036215 (1991-07-01), Masleid et al.
patent: 5040139 (1991-08-01), Tran
H. Hnatek, User's Guidebook To Digital CMOS Circuits (McGraw-Hill 1981) pp. 34-41.
R. R. Shively, et al., "Cascading Transmission Gates to Enhance Multiplier Performance" IEEE Transactions on Computers, vol. C-33, No. 7, Jul., 1984.
K. Yano, et al., "A 3.8 ns 16.times.16 Multiplier Using Complementary Pass Transistor Logic" IEEE 1989 Custom Integrated Circuits Conference.
LandOfFree
Transmission gate logic design method does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Transmission gate logic design method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Transmission gate logic design method will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-541350