Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
1999-05-05
2001-02-27
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S535000, C327S537000, C327S436000, C327S437000
Reexamination Certificate
active
06194952
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a transmission gate circuit in a semiconductor integrated circuit and, more particularly, to a transmission gate circuit having a function of compensating variations in resistance value by a body effect.
Electronic devices such as a computer and controller incorporate a plurality of circuit boards, which are connected to a common bus line. In this case, each circuit board comprises a transmission gate circuit and is connected to the common bus line via the transmission gate circuit. Each circuit board exchanges signals with the bus line via the transmission gate circuit to transmit/receive signals between circuit boards.
FIG. 21
shows the arrangement of transmission gate circuits
2
and
3
associated with the present invention, that are connected to a bus line BL. The transmission gate circuits
2
and
3
are respectively connected to circuit boards which transmit/receive signals via the transmission gate circuits
2
and
3
and bus line BL.
The back gate of an NMOS transistor is biased to the ground potential, unless otherwise specified.
Both the transmission gate circuits
2
and
3
have a CMOS structure and operate as complementary switches. Thus, the ON resistance can be decreased over the voltage range in use from the ground voltage Vss to the power supply voltage Vcc. The transmission gate circuit
3
is an analog switch having the most basic structure. This analog switch comprises n- and p-channel MOS transistors HN
1
and HP
1
. The analog switch has one terminal connected to an input terminal IN
2
, and the other terminal connected to an output terminal OUT
2
. The gate of the transistor HN
1
receives a signal generated by inputting an enable signal /EN
2
to inverters INV
4
and INV
3
, and the gate of the transistor HP
1
receives a signal output from the inverter INV
4
. Since the input and output terminals IN
2
and OUT
2
function as input/output terminals, they are used not only when a signal is transferred from a circuit (not shown) to the bus line BL but also when a signal is transferred from the bus line BL to the circuit (not shown). The back gate of the transistor HN
1
is grounded, whereas the back gate of the transistor HP
1
is connected to the power supply voltage Vcc terminal. When the enable signal /EN
2
is at high level, the transmission gate circuit
3
is turned into a conductive state to electrically connect the input and output terminals IN
2
and OUT
2
; when the signal /EN
2
is at low level, it changes to a non-conductive state.
The transmission gate circuit
2
comprises a switch SW for switching (between the power supply voltage vcc terminal or ground terminal) and a power supply terminal
10
, and is turned on when the power supply terminal
10
is connected to the power supply voltage Vcc terminal. At this time, the power supply voltage Vcc is supplied to inverters INV
1
and INV
2
and the power-supply-side terminal of a transistor P
3
. When the power supply terminal
10
is connected to the ground terminal, the circuit
2
does not receive any power supply voltage vcc and is turned off.
The transmission gate circuit
2
comprises a body effect compensation circuit in addition to an analog switch which is made up of p- and n-channel MOS transistors P
1
and N
1
each having one terminal connected to a terminal A connected to an input terminal IN
1
, and the other terminal connected to a terminal B connected to an output terminal OUT
1
connected to the bus line BL. As a body effect compensation circuit for the p-channel MOS transistor P
1
, the transmission gate circuit
2
comprises a switch made up of p- and n-channel MOS transistors P
1
P and N
1
P, a switch made up of p- and n-channel MOS transistors P
2
P and N
2
P, and the transistor P
3
used for connection to the power supply terminal
10
in the non-conductive state. The switch made up of the transistors P
1
P and N
1
P has one terminal connected to the terminal A and the other terminal connected to a back gate Nw of the transistor P
1
. The switch made up of the transistors P
2
P and N
2
P has one terminal connected to the back gate Nw of the transistor P
1
and the other terminal connected to the terminal B. The transistor P
3
has one terminal connected to the back gate Nw and the other terminal connected to the power supply terminal
10
.
As a body effect compensation circuit for the n-channel MOS transistor N
1
, the transmission gate circuit
2
comprises a switch made up of n- and p-channel MOS transistors N
1
N and P
1
N, a switch made up of n- and p-channel MOS transistors N
2
N and P
2
N, and an n-channel MOS transistor N
2
used for connection to the ground terminal in the non-conductive state. The switch made up of the transistors P
1
N and N
1
N has one terminal connected to the terminal A and the other terminal connected to a back gate Pw of the transistor N
1
. The switch made up of the transistors P
2
N and N
2
N has one terminal connected to the back gate Pw of the transistor N
1
and the other terminal connected to the terminal B. The transistor N
2
has one terminal connected to the back gate Pw of the transistor N
1
and the other terminal grounded.
When the power supply voltage Vcc terminal is connected to the power supply terminal
10
by the switch SW and the transmission gate circuit
2
is in the conductive state, the circuit
2
operates as follows. When an enable signal /EN
1
is at high level, a signal EN
1
inverted by the inverter INV
1
is input to the gates of the transistors P
1
, P
1
P, P
2
P, P
1
N, and P
2
N to turn them into the conductive state, and the signal /EN
1
is input to the gates of the transistors N
1
, N
1
P, N
2
P, N
1
N, and N
2
N to turn them conductive. Then, the terminals A and B are electrically connected, and both the transistors P
3
and N
2
are turned non-conductive.
Since the transistors P
1
P, N
1
P, P
2
P, and N
2
P are turned conductive, the source and back gate Nw of the transistor P
1
are short-circuited to compensate for the body effect on the transistor P
1
. Since the transistors P
1
N, N
1
N, P
2
N, and N
2
N are turned conductive, the source and back gate Pw of the transistor N
1
are short-circuited to compensate for the body effect on the transistor N
1
.
When the enable signal /EN
1
is at low level, the transistors P
1
, P
1
P, P
2
P, P
1
N, P
2
N, N
1
P, N
2
P, N
1
N, N
2
N, and N
1
are turned non-conductive to change the terminals A and B to a non-conductive state. Further, the transistors P
3
and N
2
are turned conductive so as not to float the back gates Nw and Pw. The back gate Nw is connected to the power supply voltage Vcc terminal by the transistor P
3
, and the back gate Pw is grounded by the transistor N
2
.
In the CMOS structure like the transmission gate circuit
2
, parasitic diodes by p-n junctions exist at various portions.
FIG. 22
shows the sectional structure of a transistor circuit having a CMOS structure formed on a semiconductor substrate
1
. This structure is called a triple-well structure. A deep n-well DNW is formed in the surface of the p-type semiconductor substrate
1
, a p-well DPW is formed in the n-well DNW, a p-well PW is formed adjacent to the n-well DNW, and an n-well NW is formed in the p-well PW. N-type diffusion layers ND
3
and ND
4
are formed in the surface of the deep n-well DNW, and biased to the power supply voltage Vcc by the power supply terminal
10
when the circuit
2
is in the ON state. P-type diffusion layers PD
13
and PD
14
are formed in the surface of the p-well PW and biased to the ground potential.
An NMOS region where an n-channel MOS transistor having n-type diffusion layers ND
1
and ND
2
, a gate oxide GO
1
, and a gate electrode G
1
is formed exists on the surface of the p-well DPW. In this NMOS region, p-type diffusion layers PD
1
and PD
2
are further formed as terminals of the back gate Pw of the n-channel MOS transistor, and biased to a predetermined voltage level via a terminal Vdpw when the circuit
2
is in the ON state. A PMOS region where a p-channel MOS transi
Callahan Timothy P.
Kabushiki Kaisha Toshiba
Luu An T.
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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