Transmission frame format converter circuit

Details Transmission frame format converter circuit Transmission frame format converter circuit

1997-10-29

2000-04-25

Nguyen, Chau

Multiplex communications

Communication techniques for information carried in plural...

Combining or distributing information via time channels

370521, H04J 306, H04J 300

Patent

active

060552484

ABSTRACT:
Disclosed is a transmission frame format converter circuit with a first-in-first-out(FIFO) memory where the inputting and outputting of a data signal are conducted at different clock rates, which has: a write control circuit which writes write-in data and a frame pulse which is extracted from a transmission line and indicates a head position of the write-in data in the FIFO memory; and a read control circuit which judges that read-out data are valid only when the frame pulse to be read out from the read control circuit is active and then reads out the read-out data from the FIFO memory, and which judges that the read-out data are invalid and then conducts the resetting of the write control circuit and the FIFO memory.

REFERENCES:
patent: 5134702 (1992-07-01), Charych et al.
patent: 5146477 (1992-09-01), Cantoni et al.
patent: 5325179 (1994-06-01), Azar et al.
patent: 5351238 (1994-09-01), Ashi et al.
patent: 5359605 (1994-10-01), Urbansky et al.
patent: 5420894 (1995-05-01), Boslough et al.
patent: 5452235 (1995-09-01), Isani
patent: 5471510 (1995-11-01), Renault et al.
patent: 5822327 (1996-06-01), Satou

Affiliated with

Also associated with

Rating

Transmission frame format converter circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Transmission frame format converter circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Transmission frame format converter circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-999416