Translator having segment bounds encoding for storage in a TLB

Details Translator having segment bounds encoding for storage in a TLB Translator having segment bounds encoding for storage in a TLB

1995-05-08

1997-07-29

Teska, Kevin J.

395417, 395800, G06F 1210

Patent

active

056528728

ABSTRACT:
A computer system emulates segment bounds checking with a paging system. Pages entirely within a segment are designated as `clear pages`, while the first and last pages containing segment bounds may be partially-valid pages. The computer system has a memory with a segment descriptor table and an active segment descriptor cache. The active segment descriptor cache holds a copy of the segment descriptors for the active segments in a central processing unit (CPU). The active segment descriptor cache also hold the first and last clear page numbers and the first and last linear address offsets for the active segment. A software segment load routine copies portions of the segment descriptor from the segment descriptor table to the active segment descriptor cache when a user program loads a new segment. Only the segment base address is copied to the CPU die; the segment limit and selector need not be stored on the CPU die. The CPU has a translation-lookaside buffer (TLB) that includes bounds fields and a comparator for signaling when an offset portion of a linear address is outside the bound on a page. A TLB miss routine compares the linear address to the first and last clear pages in the active segment descriptor cache and loads a fully-valid page if the linear address is between the first and last clear pages, but loads the bounds field with the page offset of the segment bound if the linear address is to a partial page at the bounds of the segment.

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