Translator circuit with symmetrical switching delays

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Slope control of leading or trailing edge of rectangular or...

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327318, 326 73, H03K 508, H03K 190175, H03K 512

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active

054690978

ABSTRACT:
A translator circuit for providing symmetrical switching delays for use with a power line for a differential amplifier having a first signal line and a complementary second signal line, the translator circuit including: a first voltage clamp coupled to the first signal line and to the power line for limiting a voltage differential between the power line and the first signal line; and a second voltage clamp coupled to the power line and the second signal line for limiting a voltage differential between the power line and the second signal line. The translator circuit provides reduced sensitivity to variations in process parameters, power supply voltages, temperature and manufacturing tolerances. The translator circuit also provides symmetrical tracking between the rise to rise and the fall to fall delays of an emitter coupled logic to complementary metal-oxide semiconductor translator circuit.

REFERENCES:
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patent: 4647799 (1987-03-01), Hsu
patent: 4797583 (1989-01-01), Ueno
patent: 4812676 (1989-03-01), Yang
patent: 4849659 (1989-07-01), West
patent: 5148061 (1992-09-01), Hsueh
patent: 5248909 (1993-09-01), Aoki
patent: 5283482 (1994-02-01), Chen
patent: 5315179 (1994-05-01), Pelley

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