Patent
1995-12-13
1997-06-17
Chan, Eddie P.
395417, G06F 1212
Patent
active
056405332
ABSTRACT:
An improved method and apparatus for utilizing Translation Lookaside Buffers (TLB) for maintaining page tables in a paging unit on a computer system. TLB contents for executing tasks are retained when the task is swapped out. The contents are then reloaded into the TLB when the task is again scheduled for execution. Spare memory cycles are utilized to transfer outgoing TLB data into memory, and incoming TLB data for a next scheduled task from memory.
REFERENCES:
patent: 4068303 (1978-01-01), Morita
patent: 4638426 (1987-01-01), Chang et al.
patent: 4654777 (1987-03-01), Nakamura
patent: 4714993 (1987-12-01), Livingston et al.
patent: 5025366 (1991-06-01), Baror
patent: 5060137 (1991-10-01), Bryg et al.
patent: 5317705 (1994-05-01), Gannon et al.
patent: 5440717 (1995-08-01), Bosshart
Smith, Alan Jay, "Cache Memories", Computing Surveys, vol. 14, No. 3, Sep. 1982, pp. 473-530.
Motorola, "MC88200 Cache/Memory Management Unit User's Manual", pp. 2-1 to 2-34, 1988.
Hays Kirk
Smith Wayne D.
Chan Eddie P.
Ellis Kevin L.
Intel Corporation
LandOfFree
Translation lookaside buffer (TLB) arrangement wherein the TLB c does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Translation lookaside buffer (TLB) arrangement wherein the TLB c, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Translation lookaside buffer (TLB) arrangement wherein the TLB c will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2165092