Boots – shoes – and leggings
Patent
1989-10-20
1992-09-15
Chan, Eddie P.
Boots, shoes, and leggings
395375, 364DIG1, 36424341, 3642564, 3642631, G06F 938, G06F 1210
Patent
active
051485389
ABSTRACT:
This invention implements a cache access system that shortens the address generation machine cycle of a digital computer, while simultaneously avoiding the synonym problem of logical addressing. The invention is based on the concept of predicting what the real address used in the cache memory will be, independent of the generation of the logical address. The prediction involves recalling the last real address used to access the cache memory for a particular instruction, and then using that real address to access the cache memory. Incorrect guesses are corrected and kept to a minimum through monitoring the history of instructions and real addresses called for in the computer. This allows the cache memory to retrieve the information faster than waiting for the virtual address to be generated and then translating the virtual address into a real address. The address generation machine cycle is faster because the delays associated with the adder of the virtual address generation means and the translation buffer are bypassed.
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Celtruda Joseph O.
Hua Kein A.
Hunt Anderson H.
Liu Lishing
Peir Jih-Kwon
Chan Eddie P.
Flynn John D.
Harper Blaney
International Business Machines - Corporation
Klitzman Maurice H.
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