Data processing: software development – installation – and managem – Software program development tool – Translation of code
Reexamination Certificate
2000-03-30
2003-07-15
Kim, Kenneth S. (Department: 2183)
Data processing: software development, installation, and managem
Software program development tool
Translation of code
C703S026000, C717S138000, C717S139000
Reexamination Certificate
active
06594821
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to computer systems and, more particularly, to methods and apparatus for assuring consistency of translated instructions being executed by a microprocessor which dynamically translates instructions from a target to a host instruction set.
2. History of the Prior Art
Recently, a new microprocessor was developed which combines a simple but very fast host processor (called a “morph host”) and software (referred to as “code morphing software”) to execute application programs designed for a processor having an instruction set different than the instruction set of the morph host processor. The morph host processor executes the code morphing software which translates the application programs dynamically into host processor instructions that are able to accomplish the purpose of the original software. As the instructions are translated, they are stored in a translation buffer where they may be executed without further translation. Although the initial translation of a program is slow, once translated, many of the steps normally required for hardware to execute a program are eliminated. The new microprocessor has proven able to execute translated “target” programs as fast as the “target” processor for which the programs were designed.
The morph host processor includes a number of hardware enhancements which allow sequences of target instructions spanning known states of the target processor to be translated into host instructions, stored for further use in the translation buffer, and tested to determine if the translated instructions will execute correctly. These hardware enhancements allow the buffering of the effects of execution of translations until execution has succeeded. Memory stores and target processor state are updated upon successful execution in a process referred as “committing.” These hardware enhancements allow the rapid and accurate handling of exceptions which occur during the execution of the sequences of host instructions by returning execution to the beginning of a sequence of instructions at which known state of the target processor exists. Returning the operations to a point in execution at which target state is known is called “rollback.” The new microprocessor is described in detail in U.S. Pat. No. 5,832,205, Memory Controller For A Microprocessor For Detecting A Failure Of Speculation On The Physical Nature Of A Component Being Addressed, Kelly et al, Nov. 3, 1998, assigned to the assignee of the present invention.
One problem which can arise with the new processor is that it is possible with some target programs to write to target instructions stored in memory. If this happens, the host instructions which are translations of the target instructions which have been overwritten may no longer be valid. In order to assure that invalid host translations are not executed, the new processor utilizes an indicator termed a “T bit.” A T bit is set to indicate a physical page address in memory which stores target instructions which have been translated into host instructions. If a write is attempted to a memory page protected by a T bit, a T bit exception is generated. A T bit exception causes an exception handler to look up a data structure which holds references to addresses of host instructions translated from the target instructions on the page protected by the T bit. The exception handler invalidates these host translations and turns off the T bit protection for the memory page. The arrangement for utilizing T bits is described in detail in U.S. patent application Ser. No. 08/702,771, entitled Translated Memory Protection Apparatus For An Advanced Microprocessor, Kelly et al, filed Aug. 22, 1996, now U.S. Pat. No. 6,199,152, and assigned to the assignee of the present invention.
The arrangement which utilizes T bits to indicate memory pages storing target instructions which have been translated was refined to address problems in operation which occurred in translating programs designed for target processors employing operating systems which do not discriminate between areas in which instructions and data are stored. For example, Microsoft Windows allows instructions and data to be stored on the same memory pages. When an attempt is made to write to data on a memory page protected by the T bit arrangement described above, a T bit fault occurs. The resulting exception causes all translations of target instructions on the protected memory page to be invalidated even though a write to data does not change any target instruction. Similarly, an attempt to write to one target instruction on a memory page does not affect the validity of translations from other target instructions stored on the same memory page. Invalidating correct translations on a memory page protected by a T bit significantly slows the operation of the new microprocessor.
In order to overcome these difficulties, a process which allows finer grain discrimination between memory areas storing data and areas storing target instructions was implemented. The improved process detects writes to a memory page storing target instructions which have been translated to host instructions, detects whether a sub-area of the memory page to which a write is addressed stores target instructions that have been translated, and invalidates host instructions translated from target instructions at an addressed protected sub-area. The process improves the operational speed of the new microprocessor by eliminating the invalidation of translations which are not affected by writes to memory pages protected by T bits and reduces the number of T bit traps taken that do not cause invalidation of translations. The process is described in detail in U.S. patent application Ser. No. 09/417,356, entitled Fine Grain Translation Discrimination, Banning et al, filed Oct. 13, 1999, now issued U.S. Pat. No. 6,363,336, and assigned to the assignee of the present invention.
Although the improved arrangement functions quite well in most circumstances, there are situations in which additional improvement is desirable. For example, there are situations in which a write to a memory address having fine grain T bit protection initiates the T bit process to invalidate a translation even though the write is to a portion of the memory sub-area which stores data. This occurs because the sub-areas protected by fine grain T bits are still larger than the area which may be addressed. There are other situations in which a data portion of an instruction is constantly being changed although the instruction is not. Other situations also arise in which fine grain T bit protection causes system operation to slow significantly. For example, sometimes T bit exceptions generated by writes to particular sub-areas occur so frequently that the T bit method of invalidating translations simply slows the system too much.
It is desirable to increase the computer system operating speed by improving the operation of the system for assuring the consistency of translations of instructions.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to improve the operating speed of a microprocessor capable of running programs designed for other microprocessors while maintaining consistency between target instructions and host translations of those target instructions.
This and other objects of the present invention are realized by a method for determining whether target instructions which have been translated to host instructions have changed since being translated, including the steps of storing a copy of a target instruction which has been translated to host instructions, comparing the copy of the target instruction which has been translated with data at a memory address at which the target instruction was stored when translated when an attempt to execute the host instructions occurs, and invalidating host instructions translated from a target instruction if the data at the memory address and the copy of the target instruction differ.
REFERENCES:
patent: 5832205 (1998-11-01), K
Anvin H. Peter
Banning John
Bedichek Robert
Rozas Guillermo J.
Shaw Andrew
Kim Kenneth S.
Transmeta Corporation
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