Miscellaneous active electrical nonlinear devices – circuits – and – Gating – Utilizing three or more electrode solid-state device
Reexamination Certificate
2000-12-15
2002-08-13
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Gating
Utilizing three or more electrode solid-state device
C327S387000, C327S389000, C326S057000
Reexamination Certificate
active
06433613
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to circuitry for switching electrical signals transmitted from one location to another. More particularly, the present invention relates to switch circuitry for translating electrical signals at a first potential into corresponding electrical signals at a second potential different from the first potential. The present invention includes a disablement option for selective activation of the translation switch circuitry.
2. Description of the Prior Art
Output buffers are used to transfer electrical signals of desired amplitude and strength. Signal transfers occur by way of buses—interfaces that couple together active devices that are either on the same semiconductor-based chip or on different chips. The devices may be located proximate to one another, or they may be some relative distance from one another. Among other uses, output buffers including those employed to translate electrical signals on a particular computing system board or among a plurality of circuit boards of a computing system.
Developments in semiconductor technology have created the capability to produce low-cost, highly reliable switches that are, effectively, implementations of mechanical relays. They have been found to be of particular use, when implemented, as single pole, single throw, type relays, but are not limited thereto. Semiconductor switches are used as replacements for the prior mechanical relays, due to the high switching speed available as well as their ability to transfer relatively high currents without failure. These switches are often referred to as transfer gates or pass transistors as they employ the characteristics of transistors—usually MOS transistors—to either permit or prevent the passage of a signal.
It is well known that semiconductor switches are widely used in many fields. They are used in all variety of large- and small-scale consumer products, including, but not limited to, automobiles and home electronics. They can be and are used as analog routers, gates, and relays. They are used as digital multiplexers, routers, and gates as well.
A number of prior-art transfer gates or semiconductor switches have been developed for digital and analog applications. These switches are increasingly being called upon to transfer electrical signals to systems that are powered by power supplies at potentials different from the potentials associated with the input electrical signals. As a result, it is necessary to have switches that can convert or translate electrical signals at one potential to corresponding signals at a different potential, at least with respect to the potential associated with a logic HIGH. As is well known by those in this field, the difference in the potentials associated with a logic HIGH signal and a logic LOW signal may be as small as 0.4V or as great as 5V. For Complementary Metal Oxide Semiconductor (CMOS) based logic for example, a logic high corresponds to a nominal 5.0V potential (for a 5.0V power supply) and a nominal 3.3V potential (for a 3.3V power supply), while a logic low is essentially equivalent to ground (GND) or 0.0V.
The potentials associated with HIGH and LOW signals described above are idealized values. In fact, the signal potentials generally fall within a range of potentials associated with the indicated values. Thus, for a 3.3V supply, a HIGH signal may be supplied at 2.6V, for example, while a LOW signal may actually be associated with a 0.7V value. As the potentials of the power supplies used to power circuitry move closer to GND, variations in signal potentials are more likely to produce transmission glitches. It is therefore desirable to maintain signal potentials as stable as possible. Alternatively or in addition, it is important to design the semiconductor switch to be less sensitive to signal variations but without sacrificing operating capability, i.e., propagation rates and signal amplitudes. This is particularly noteworthy for translation circuitry where the disparity in logic HIGH potentials can be on the order of 1.7V as indicated above.
One example of a typical potential translating bus switch is shown in FIG.
1
. The bus
1
includes a set of
12
switch structures SW
1
-SW
12
, each of which is designed to transfer a bit of information from individual input nodes a
1
-a
12
to corresponding individual output nodes b
1
-b
12
. Nodes a
1
-a
12
are coupled to extended circuitry (not shown) having a power supply at a first potential and nodes b
1
-b
12
are coupled to extended circuitry (not shown) having a power supply at a potential less than that of the extended circuitry coupled to nodes a
1
-a
12
. Of course, it is to be understood that the bus may comprise more or fewer switch sets as a function of the number of bits to be propagated.
As illustrated in
FIG. 2
, an exemplar one of the switch structures, switch SW
1
, is shown coupled between node a
1
and node b
1
. The other switch structures may be similarly configured. Extended circuitry coupled to node a
1
is powered by a high-potential supply Vcc
1
and extended circuitry coupled to node b
1
is powered by a high-potential supply Vcc
2
that is less than the potential associated with Vcc
1
. Both are coupled to a common low-potential rail GND.
The switch SW
1
includes a transfer transistor M
1
having a source coupled to node b
1
and a drain coupled to node a
1
. The transistor M
1
is preferably an NMOS transistor. The transfer transistor M
1
is designed, when enabled by a transfer switch-enabling signal at enable node EN, to propagate electrical signals from node a
1
to node b
1
. The transfer transistor M
1
includes a bulk or backwell coupled to a low-potential power rail GND that is common to the extended circuitry associated with nodes a
1
and b
1
. The switch SW
1
further includes a first inverter IV
1
and a second inverter IV
2
. The first inverter IV
1
is coupled between Vcc
1
and GND and includes an input coupled to node EN. Second inverter IV
2
includes a complementary pair of inverter transistors M
2
and M
3
. Transistor M
2
is a PMOS transistor having a gate coupled to the output of IV
1
, a source coupled to a pseudo high-potential power rail Prail, and a drain that is, effectively, node C. Transistor M
3
is an NMOS transistor having its gate also coupled to the output of IV
1
, its source coupled to GND, and its drain coupled to node C. The potential of Prail establishes the potential of the output of IV
2
to the gate of M
1
and so by definition is less than the potential of Vcc
1
.
With continuing reference to
FIG. 2
, the potential of Prail is established in the prior art by a diode drop across diode D
1
. Diode D
1
has a high potential node coupled to Vcc
1
and a low-potential node coupled to resistor R. The output of forward-biased diode D
1
supplies a potential to the source of M
2
that is transferred, with a second drop associated with that transistor, to the gate of M
1
. That arrangement is sufficient to produce a suitable translation of the signal potential from a
1
to b
1
.
Unfortunately, the design of the switch circuit as shown in
FIG. 2
has an important limitation if there is any interest in using the switch to propagate transient signals rather than steady state signals. Specifically, noise on Prail that changes the potential of that rail can result in translation errors at the corresponding b nodes when logic signal transitions occur. That noise is caused by multiple simultaneous logic-LOW-to-logic-HIGH transitions on the inputs al-a
12
. The noise causes current to be injected onto Prail through the drain/gate capacitance of the corresponding large transfer transistor represented by transistor M
1
in FIG.
2
. As the voltage on one side of the effective capacitor of that transistor changes, the voltage on the other side of the capacitor also changes—unless it is fixed to a power rail or a voltage reference.
Diode D
1
will not restrict the voltage changing on the gate of transistor M
1
. Resistance R acts to restrict the voltage change in
Boomer James
Goodell Trenor
Callahan Timothy P.
Cesari and McKenna LLP
Fairchild Semiconductor Corporation
Nguyen Minh
Paul, Esq. Edwin H.
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