Translating a dynamic transfer control instruction address in a

Details Translating a dynamic transfer control instruction address in a Translating a dynamic transfer control instruction address in a

1990-12-07

1992-11-24

Kriess, Kevin A.

Boots, shoes, and leggings

395500, 364DIG1, 3642323, 3642624, 3642476, 364247, 3642477, 3642629, G06F 930

Patent

active

051670232

ABSTRACT:
The system and method of this invention simulates the flow of control of an application program targeted for a specific instruction set of a specific processor by utilizing a simulator running on a second processing system having a second processor with a different instruction set. The simulator reduces the number of translated instructions needed to simulate the flow of control of the first processor instructions when translating the address of the next executable instruction resulting from a dynamic transfer of control, i.e., resulting from a return instruction. The simulator compares the address that is loaded at run time by the return instruction with the return address previously executed by that instruction. If the last return address matches, the location of the return is the same. If the last return does not match, a translate look-aside buffer is used to determine the address. If the translate look-aside buffer does not find the address, then a binary tree look up mechanism is used to determine the address of the next instruction after a return. The performance of the simulator is enhanced by utilizing the easiest approaches first in the chance that a translated instruction will result most efficiently.

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