Transition encoded dynamic bus circuit

Details Transition encoded dynamic bus circuit Transition encoded dynamic bus circuit

2007-01-09

2007-01-09

Bocure, Tesfaldet (Department: 2611)

Pulse or digital communications

Receivers

C375S340000, C326S038000, C326S098000

Reexamination Certificate

active

10035574

ABSTRACT:
A transition encoded dynamic bus includes an encoder circuit at the input to the bus and a decoder circuit at the output to the bus. The encoder circuit generates a signal indicative of a transition at the input to the bus rather than the actual value at the input. The decoder circuit decodes the transition encoded information to track the appropriate value to be output from the bus.

REFERENCES:
patent: 3820031 (1974-06-01), Smithlin
patent: 3967061 (1976-06-01), Dobias
patent: 4229823 (1980-10-01), Thomson et al.
patent: 4453229 (1984-06-01), Schaire
patent: 4525848 (1985-06-01), Simpson
patent: 4663767 (1987-05-01), Bodlaj et al.
patent: 5646557 (1997-07-01), Runyon et al.
patent: 6005417 (1999-12-01), Mehta et al.
patent: 6028814 (2000-02-01), Lim
patent: 6140843 (2000-10-01), Howard
patent: 6188596 (2001-02-01), Holst
patent: 6333645 (2001-12-01), Kanetani et al.
patent: 6351150 (2002-02-01), Krishnamurthy et al.
patent: 6417698 (2002-07-01), Williams et al.
patent: 6453399 (2002-09-01), Wada
patent: 6559680 (2003-05-01), Bhushan et al.
patent: 6717448 (2004-04-01), Heo et al.
patent: 6741094 (2004-05-01), Ogawa
patent: 6765408 (2004-07-01), Cheng et al.
patent: 6894536 (2005-05-01), Martin et al.
patent: 6990035 (2006-01-01), Redwine et al.
patent: 2001/0052797 (2001-12-01), Bhushan et al.
patent: 2003/0001184 (2003-01-01), Anders et al.
patent: 2003/0107411 (2003-06-01), Martin et al.
patent: 2005/0146357 (2005-07-01), Anders et al.
patent: 2005/0285631 (2005-12-01), Goldman et al.
patent: 2006/0140034 (2006-06-01), Hsu et al.
Burleson et al.; Low-Power Encodings for Global Communication in CMOS VLSI; IEEE Transactions on Very Large Scale Integration (VLSI) Systems; vol. 5, No. 4; Dec. 1997; pp. 444-455.
Burleson et al.; Coding a Terminated Bus for Low Power; 1995. Proceedings., Fifth Great Lakes Symposium on VLSI Mar. 16-18, 1995 pp. 70-73.
Burleson et al.; Bus-Invert Coding Low-Power I/O; IEEE Transactions on Very Large Scale Integration (VLSI) Systems; vol. 5, No. 4; Dec. 1997; pp. 49-58.
Anders, Mark, et al., “A Transition-Encoded Dynamic Bus Technique for High-Performance Interconnects”, Symposium on VLSI Circuits. Digest of Technical Papers, pp. 16-17 (Jun. 13-15, 2002).
Anders, Mark, et al., “A Transition-Encoded Dynamic Bus Technique for High-Performance Interconnects”, IEEE Journal of Solid-State Circuits, vol. 38, No. 5, pp. 709-714 (May 2003).
Stan, Mircea R., et al., “Bus-Invert Coding for Low-Power I/O”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 3, No. 1, pp. 49-58 (Mar. 1995).
Hsu et al—U.S. Appl. No. 11/025,778 entitled Transition-Encoder Sense Amplifier filed Dec. 29, 2004.

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