Transition-based wired "OR" for VLSI systems

Details Transition-based wired "OR" for VLSI systems Transition-based wired "OR" for VLSI systems

1991-10-07

1992-10-06

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307475, 307465, 307353, 307358, H03K 1716, H03K 5153

Patent

active

051534550

ABSTRACT:
A transition-based wired "OR" bus circuit for use on a VLSI system including a common bus line and a plurality of I.C. chips connected to the bus line permits interchip communication among the plurality of interconnected I.C. chips upon a digital bus line. The bus circuit includes an output driver stage, a sampling/hold circuit, and control logic circuitry. The control logic circuitry causes a toggle signal on the bus line to be driven to a value in the present cycle to be different from than sampled in the prior sample so as to indicate an assertion. The sampling/hold circuit generates a toggle-based "OR" resultant signal which is maintained at a high logic level only when the value sampled during the present cycle is different from the value sampled in the prior cycle. The bus circuit eliminates the use of any external components, has reduced power consumption, and has a high speed of operation.

REFERENCES:
patent: 4463272 (1984-07-01), Tucker
patent: 4749879 (1988-06-01), Peterson et al.
patent: 4866300 (1989-09-01), Bolk et al.
patent: 5116342 (1992-05-01), Schmidt et al.

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