Transistors using crystalline silicon devices on glass

Details Transistors using crystalline silicon devices on glass Transistors using crystalline silicon devices on glass

1993-10-18

1995-05-09

Limanek, Robert P.

Active solid-state devices (e.g., transistors, solid-state diode

Non-single crystal, or recrystallized, semiconductor...

Amorphous semiconductor material

437 86, H01L 2904, H01L 2978

Patent

active

054142768

ABSTRACT:
A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed.

REFERENCES:
patent: 3332137 (1967-07-01), Kenney
patent: 3959045 (1976-05-01), Antypas
patent: 4601779 (1986-07-01), Abernathey et al.
patent: 5013681 (1991-05-01), Godbey et al.
patent: 5110748 (1992-05-01), Sarma
patent: 5264721 (1993-11-01), Gotou
patent: 5266825 (1993-11-01), Isukada et al.
patent: 5289030 (1994-02-01), Yamazaki et al.
R. A. Lemons et al. "Laser Crystallization On Si Films On Glass", Appl. Phys. Lett., vol. 40, pp. 469-471, 1982.
J. B. Laskey et al., "Silicon-on-Insulator (SOI) by Bonding and Etch-back", Dig. 1985 IEEE Int. Electron Devices Mtng., Dec. 1985, pp. 684-687.
L. J. Spangler et al., "A Technology for High-Performance Single-Crystal Silicon-on-Insulator Transistors", IEEE Elec. Device Lett., vol. EDL-8, No. 4, Apr. 1987, pp. 137-139.
T. W. Sigmon et al., "Nanosecond Thermal Processing for Ultra-High-Speed Device Technology", Mat. Res. Soc. Symp. Proc., vol. 158, 1990, pp. 241-253.
K. H. Weiner et al., "Low-Temperature Fabrication of p+-NDiodes with 300-.ANG. Junction Depth," IEEE Electron Device Letters, vol. 13, No. 7, Jul. 1992, pp. 369-371.
D. J. Frank et al., "Monte Carlo S.imulation of a 30nm Dual-Gate MOS FET: How Short Can Si Go?", IEEE, IEDM 92-553, Dec. 1992, pp. 21.1.1-21.1.4.

Affiliated with

Also associated with

Rating

Transistors using crystalline silicon devices on glass does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Transistors using crystalline silicon devices on glass, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Transistors using crystalline silicon devices on glass will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1708054