Transistorized focal plane having floating gate output nodes

Details Transistorized focal plane having floating gate output nodes Transistorized focal plane having floating gate output nodes

1981-12-28

1984-04-24

Yusko, Donald J.

Communications: electrical

Continuously variable indicating

With meter reading

358212, H04Q 900, H04N 312, H04J 4014

Patent

active

044451172

ABSTRACT:
A transistorized monolithic focal plane array is formed on a semiconductive substrate and comprises a plurality of detectors associated with a corresponding plurality of source follower or inverter transistors. The array is row addressable. The gate of the source follower transistor comprises a floating node which is charged by the corresponding detector in proportion to the incident photon flux, the gate being periodically reset. The invention combines the advantages of compactness and low capacitance of charge coupled device imagers and low noise characteristics of prior art imagers comprising discrete transistors.

REFERENCES:
patent: 4107474 (1978-08-01), Schneider
patent: 4274113 (1981-06-01), Ohba et al.
patent: 4385321 (1983-05-01), Malm
patent: 4390791 (1983-06-01), Hatanaka et al.

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