Transistorised memory cell and an integrated memory using such a

Details Transistorised memory cell and an integrated memory using such a Transistorised memory cell and an integrated memory using such a

1975-03-21

1976-05-04

Hecker, Stuart N.

Communications: electrical

Digital comparator systems

307291, G11C 1140

Patent

active

039551822

ABSTRACT:
A memory cell as required for use in the building of integrated memories, which contains bistable trigger stages formed by two transistors, with a high operational reliability, a low power consumption and an access time of less than 0.01 microseconds for a store of 64 elements, is provided. To this end, low-consumption field-effect transistors are chosen, obtained by the ion implantation of an N-type channel, in order, in each cell, to form, in addition to the two transistors of the trigger stage, a pair of transistors connected as amplifier-followers. The selection of a cell is effected by raising the potential on the word line connected to the sources of the transistors of the trigger stage.

REFERENCES:
patent: 3633182 (1972-01-01), Koo
patent: 3668656 (1972-06-01), Hoggar
Palfi, Bilevel Powered FET Memory Cell, IBM Technical Disclosure Bulletin, Vol. 14, No. 1, 6/71, pp. 261-262.

Affiliated with

Also associated with

Rating

Transistorised memory cell and an integrated memory using such a does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Transistorised memory cell and an integrated memory using such a, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Transistorised memory cell and an integrated memory using such a will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-683103