Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2001-12-27
2002-11-05
Ngô, Nân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S341000, C257S578000, C257S579000, C257S584000, C257S654000, C257S786000
Reexamination Certificate
active
06476495
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor device used for a transistor such as a bipolar transistor, MOS transistor, IGBT, etc., and more particularly to a transistor which can minimize the DC resistance of the wiring and lead formed on a semiconductor chip, thereby giving a large current at a low voltage.
2. Description of the Related Art
The bipolar transistor provides a corrector current which depends on the area and circumferential length of an emitter. Therefore, in order to acquire a large current, emitter regions are preferably distributed in a base region. For this purpose, a large number of cells constituting transistor units are distributed in a “stripe emitter structure”, “multi-emitter structure” or “multi-base structure”. An emitter electrode
1
and a base electrode
2
are formed so that they are connected to the respective cells. As seen from perspective views of FIGS.
3
(
a
) and
3
(
b
) in which the package is removed. The respective electrodes
1
and
2
are formed to constitute comb teeth which are in mesh with each other.
As the MOS transistor, a vertical MOS transistor and double-diffused MOSFET are known for use in a large current. In both MOSFETs, body regions which serve as cell regions are formed in a matrix shape, source electrodes are formed to be connected to the source regions formed within the respective body regions, and a source electrode pad and a gate electrode pad are formed on a semiconductor chip surface. In the case of the MOSFET, the gate electrodes in the respective cells and a gate wiring which connects these gate electrodes to one another are formed of poly-Si which belong a different layer from the source wiring of a metallic film such as Al. As the case may be, the gate electrodes are connected partially by a metallic wiring serving as a gate finger.
In order to improve the current characteristic of such a semiconductor chip, its area within a package must be maximized. For example, in SC-59 (trade name), the molding part of the package is rectangular so that the planar shape of the semiconductor chip is also rectangular. As seen from FIG.
3
(
a
), the emitter electrode
1
and base electrode
2
are formed so that their teeth extend along the short side of a rectangle. Their electrode pads
1
a
and
2
a
are formed centrally in the long side of the rectangle. A semiconductor chip
10
is die-bonded on a rectangular die pad so that a collector electrode
3
formed on the rear surface of the semiconductor chip
10
is electrically connected to a third lead
6
. An emitter electrode pad
1
a
and a first lead
4
are connected by a wire
7
of e.g. gold and an base electrode pad
2
a
and a second lead
5
are also connected by the wire
7
. The periphery of the semiconductor chip is covered with molding resin as indicated in one-dot chain line.
In this structure, since the electrodes at the center on the semiconductor chip and the leads on both ends thereof are connected by wires, respectively, the length L of each wire is increased. Therefore, its resistance will disadvantageously boost the collector-emitter voltage.
On the other hand, as seen from FIG.
3
(
b
), where the electrode pattern on the semiconductor chip
10
is formed so that comb teeth extend along a long side of a rectangle of the semiconductor chip
10
, their electrodes
1
a
and
2
a
are approximate to the second leads
4
and
5
so that the former can be connected to the latter via a short wire
7
. However, this structure lengthens the length L
2
of the wiring pattern on the semiconductor chip so that the resistance of the metallic film wiring which is formed of a thin film cannot be disregarded for a large current. Further, in the MOSFET, connection of gate electrodes by a poly-Si film presents a problem that the signal transmission speed to a cell far from the electrode pad is retarded.
As described above, in the transistor for use in a large current in which a large number of cells constituting transistor units in a semiconductor chip are formed and an electrode wiring is formed to be connected to the respective cells, the position of the electrode pads and the resistance of the wire for connecting the electrode pad and the external lead greatly influence the characteristic of the transistor. This presents problem that a large current cannot be acquired at a low operation voltage.
Further, in order to reduce the resistance of the electrode wiring on the semiconductor chip, the wiring is formed in double layers to increase the wiring area. However, forming the double layers presents a problem that the number of the steps for manufacturing the semiconductor chip is increased and the production cost is raised.
SUMMARY OF THE INVENTION
This invention has been accomplished in order to solve the problems described above. An object of this invention is to provide a transistor which can reduce the resistance of an electrode wiring and a connecting portion to an external lead so that a large current can be acquired at a low operation voltage.
The transistor according to this invention comprises a semiconductor chip in which a large number of cells constituting transistor units are arranged on a planar and rectangular semiconductor substrate, on the front surface of the semiconductor chip, a first electrode to be connected to an emitter or source and a second electrode to be connected to an base or gate are formed, and electrode pads of the first electrode and the second electrode are formed on opposite long sides of the rectangular substrate, and on the rear surface of the semiconductor chip, a third electrode to be connected to a collector or drain is formed; a third lead having a rectangular island to which the semiconductor chip is die-bonded and which is extended out from a long side of the island in a direction perpendicular to a long side of the island; a first and a second lead which are directly bonded to the electrode pads of the first and the second electrode; and a resin package covering the periphery of the semiconductor chip. It should be noted that the cells constituting transistor units may be formed in stripes.
In accordance with such a structure, electrode wirings formed on a semiconductor chip are short wirings extending along a short side of a rectangle so that the resistance to the cells on the edge side of the chip is not increased so greatly. Further, the electrode pads which are centrally located on the semiconductor chip are relatively apart form the first lead and the second lead. However, since the first lead and the second lead are directly connected to the electrode pads, the first lead and second lead can be sufficiently thick and give a small resistance, thereby giving rise to no increase in the driving voltage.
The first and the second lead are formed so that they are extended on both ends of the rectangular island in a direction in parallel to the third lead along the semiconductor chip from the side opposite to the the third lead, and their tip sides are bent in an L-shape toward the center of the semiconductor chip and formed in parallel to each other so that they are located at the electrode pads of the first and the second electrode, respectively. In accordance with such a configuration, where the transistors having large or small semiconductor chip sizes according to characteristics are prepared for market as a series of various kinds of products, if the semiconductor chips are manufactured with the length of the short side of the rectangle being constant and the length of the long side being variable, the transistors can be assembled in the same manufacturing process by only replacing the semiconductor chip using the same lead frame.
The transistor preferably has a structure in which the first electrode and the second electrode are an emitter electrode and a base electrode which are an emitter and a base of a bipolar transistor, respectively, and the emitter electrode and the base electrode are made of a metallic film so as to constitute comb teeth which are in mesh wit
Morgan & Lewis & Bockius, LLP
Ngô Nân V.
LandOfFree
Transistor which can minimize the DC resistance of the... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Transistor which can minimize the DC resistance of the..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Transistor which can minimize the DC resistance of the... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2933542