Transistor varactor for dynamics semiconductor storage means

Details Transistor varactor for dynamics semiconductor storage means Transistor varactor for dynamics semiconductor storage means

1987-07-16

1989-08-08

Clawson, Jr., Joseph E.

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357 41, 357 54, 357 59, 365149, 365182, H01L 2978

Patent

active

048558010

ABSTRACT:
A transistor varactor for dynamic semiconductor storage means which are formed on a doped silicon substrate having a high integration density and which includes one field effect transistor which has source and drain and a gate and a varactor overlaps the gate electrode and is formed as a stacked capacitor. The gate electrode and the varactor are electrically isolated from each other by insulating layers and the contact of the source zone is electrically isolated from the gate electrode by the insulating layers and the upper polysilicon layer of the varactor formed by oxidation of the side portions of the polysilicon layer. The contact of the source zone adjusts to the gate electrode and to the polysilicon layer in that the distance of the contact of the source zone relative to the gate electrode and the polysilicon layer is independent of the photographic accuracy. A buried contact between the polysilicon layer and the drain zone is self-adjusted relative to the gate electrode.

REFERENCES:
patent: 4356040 (1982-12-01), Fu et al.
patent: 4649406 (1987-03-01), Takemae et al.
patent: 4754313 (1988-06-01), Takemae et al.
IEEE Transactions on Electron Devices, vol. Ed-29 Mar. (1982), No. 3, New York, U.S.A.-Quadruply Self-Aligned Stacked High-Capacitance RAM Using Ta.sub.2 O.sub.5 High-Density VLSI Dynamic Memory--Ohta, Yamada, Shimizu and Tarui, pp. 368-376.
J. Sturm et al, IEEE Electron Device Letters, vol. Ed1-5, No. 5, May 1984 "A Three-Dimensional Folded Dynamic RAM in Beam-Recrystallized Polysilicon", pp. 151-153.
IEEE Journal of Solid-State Circuits, vol. SC20, No.1 Feb., A Capacitance-Coupled Bit Line Cell Taguchi, Ando, Hijiya, Nakamura, Enomoto and Yabu, pp. 210-215, Feb. 1985.
IEEE Transactions on Electron Devices, vol. ED-27, No. 8, Aug. 1980, A 5-V Only 16-kbit Stacked-Capacitor MOS RAM Koyanagi, Sakai, Ishihara, Tazunoki, Hashimoto, pp. 1596-1601.

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