Transistor-transistor logic to emitter coupled logic translator

Details Transistor-transistor logic to emitter coupled logic translator Transistor-transistor logic to emitter coupled logic translator

1985-06-04

1987-03-31

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307456, 307473, H03K 19003, H03K 19092, H03K 1760, H03K 1704

Patent

active

046545492

ABSTRACT:
A transistor-transistor logic (TTL) to emitter coupled logic (ECL) translator includes a TTL input gate for receiving TTL voltage level logic input signals in the positive voltage range compatible with TTL circuits and an ECL output gate for delivering corresponding ECL voltage level logic output signals in the negative voltage range compatible with ECL circuits. A translating current source operatively coupled between the TTL input gate and ECL output gate translates signals down to the negative ECL voltage range for application to the input transistor of the ECL output gate. A bidirectional bridge clamp also operatively coupled between the TTL input gate and ECL output gate limits the swing of the translated signals in the negative voltage range applied at the input of the ECL output gate thereby reducing propagation delay across the translator and reducing power dissipation.

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F100K ECL User's Handbook, 1982, Fairchild Camera & Instrument Corp., Advanced Bi--Polar Div., Chapter 2, "Circuit Basics".
F100K ECL Data Book,--Fairchild Camera & Instrument Corp., Advanced Bi--Polar Div., Chapter 1, "Family Overview".

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