Transistor-transistor logic circuit with hysteresis

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307360, 307443, 307458, 307264, H03K 19003, H03K 19088, H03K 1920

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045019762

ABSTRACT:
A TTL circuit having a pair of current sources (R2/V.sub.CC and R2/V.sub.CC) and a pair of transistors (Q1 and Q2) arranged in a standard TTL input/inverting configuration has hysteresis at the input signal (V.sub.X) for providing noise protection. A hysteresis circuit (10) suitably containing another current source (R3/V.sub.CC) coupled to the base of the inverting transistor (Q2) and a rectifier (12) coupled between the collector of the inverting transistor and the current source (R1/V.sub.CC) coupled to the base of the input transistor (Q1) provides the hysteresis at the circuit switching points.

REFERENCES:
patent: 3510685 (1970-05-01), Watanabe et al.
patent: 3544808 (1970-12-01), Mukai
patent: 3676713 (1972-07-01), Wiedmann
patent: 3836792 (1974-09-01), Eckert, Jr. et al.
patent: 3934157 (1976-01-01), Evans
patent: 4375598 (1983-03-01), Sakai
"Transistor-Transistor Logic with High Packing Density and Optimum Performance at High Inverse Gain," 1968, ISSCC Dig. of Tech. Paps., Feb. 15, 1968, pp. 38-39.
Montegari, "Universal Latch", IBM Tech. Disc. Bull., vol. 19, No. 10, Mar. 1977, pp. 3743-3744.

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