Transistor structure with minimized parasitics and method of...

Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Walled emitter

Reexamination Certificate

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Details

C438S366000, C257SE21371, C257SE21379

Reexamination Certificate

active

07491617

ABSTRACT:
A transistor having minimized parasitics is provided including an emitter having a recessed extrinsic emitter portion atop an intrinsic emitter portion; a base including an intrinsic base portion in electrical contact with the intrinsic emitter portion and an extrinsic base portion in electrical contact with the intrinsic base portion and electrically isolated from the recessed extrinsic emitter portion by a set of emitter/base spacers; and a collector in electrical contact with the intrinsic base portion. The transistor may further include extrinsic base having top surfaces entirely silicided to the emitter/base spacer. Additionally, the transistor may include a base window opening within the transistor's active area. Methods of forming the above-described transistor are also provided.

REFERENCES:
patent: 5962880 (1999-10-01), Oda et al.
patent: 6346453 (2002-02-01), Kovacic et al.
patent: 6753234 (2004-06-01), Naem
patent: 2001/0002061 (2001-05-01), Johnson
patent: 2003/0057458 (2003-03-01), Freeman et al.
patent: 2256242 (1990-10-01), None
patent: 11330088 (1999-11-01), None

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