Electricity: electrical systems and devices – Safety and protection of systems and devices – With specific current responsive fault sensor
Reexamination Certificate
2000-03-28
2002-05-14
Han, Jessica (Department: 2836)
Electricity: electrical systems and devices
Safety and protection of systems and devices
With specific current responsive fault sensor
Reexamination Certificate
active
06388855
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a protecting circuit of a transistor.
2. Description of the Related Art
In recent years, a gate length is reduced with the improvement of process technique, so that the switching speed of a power MOS transistor is increased. As a result, the rising edge and falling edge of output current of the power MOS transistor become steep. Therefore, in the power MOS transistor, various problems, such as the change of a power supply voltage and the radiation of noise, are caused by the steep change of the output current.
Generally, as shown in
FIGS. 1 and 2
, the gates of power MOS transistors
1
and
2
are driven with gate signals from inverters (buffers)
8
and
9
, respectively. Therefore, conventionally, the sizes of output transistors in the buffers
8
and
9
are adjusted such that output resistances are made large. Instead, high resistances
18
and
19
are inserted between the buffers
8
and
9
and the gates of the power MOS transistors
1
and
2
to make the gate signals less steep by the resistances
18
and
19
and capacitances
16
and
17
between and the gates and drains of the power MOS transistors
1
and
2
. As a result, a rising time and a falling time are made long in the output current waveforms of the power MOS transistors
1
and
2
.
However, in a first conventional example, the ability to drive the gate of the power MOS transistor is reduced. When the voltage of a load connection terminal changes by a large amount, charging and discharging currents flow through the capacitance
16
or
17
between the gate and the drain. In this case, the voltage levels a
1
′ and a
2
′, and b
1
′ and b
2
′ of the gate signals ga and gb is changed, as shown in FIG.
8
. As a result, the power MOS transistor
1
or the power MOS transistor
2
is erroneously turned on, so that the current flows between the power supply and the ground. When the gate voltages exceed the breakdown voltages of the power MOS transistors
1
and
2
, the power MOS transistors
1
and
2
are possibly destroyed.
In conjunction with the above description, an H bridge protecting circuit is known in Japanese Laid Open Patent Application (JP-A-Heisei 1-91620). In this reference, an H bridge circuit is composed of a direct current power supply and four semiconductor devices. A control circuit controls each of the four semiconductor devices to be in a conductive or non-conductive state such that a motor is rotated in a positive direction or in an reverse direction. A stopping circuit detects an over-voltage or a surge voltage generated in the direct current power supply and controls all the four semiconductor devices to set to the non-conductive state. An over-current detecting circuit detects an over-current flowing through any of the four semiconductor devices. When the over-current detecting circuit detects the over-current, the stopping circuit controls all the four semiconductor devices to set to the non-conductive state.
Also, a semiconductor circuit apparatus is known in Japanese Laid Open Patent Application (JP-A-Heisei 2-58372). In this reference, a vertical type insulating gate field effect element is used as a pull-up element, in which a semiconductor substrate is used as a drain or an anode terminal. Also, an insulating gate field effect element is used as a pull-down element, which is formed in an N-type region separated by a P-type region.
Also, a through current preventing circuit is known in Japanese Laid Open Patent Application (JP-A-Heisei 4-331492). In this reference, an H bridge circuit is composed of two P-channel MOS transistors (
9
,
10
) and two N-channel MOS transistors (
11
,
12
). A through current preventing circuit is composed of first and second buffer circuits (
16
) in which a rising time of an output signal is longer than a falling time of the output signal, third and fourth buffer circuits (
18
) in which a falling time of an output signal is longer than a rising time of the output signal, and fifth and eighth buffer circuits, (
17
,
19
) in which a rising time of an output signal is equal to a falling time of the output signal. As a result, there is no operation period of all the MOS transistors (
9
to
12
). Thus, the through current can be prevented. A high frequency operation of the H bridge circuit is made possible if the duty ratios of drive signals (
1
and
2
) are determined in consideration of a non-operation period.
Also, an electrostatic discharge(ESD) protecting circuit is known in Japanese Laid Open Patent Application (JP-A-Heisei 8-55958 corresponding to U.S. patent application No. 08/280417). In this reference, the ESD protecting circuit is composed of a first n
+
-type diode whose cathode is connected to a pad and whose anode is connected to a substrate ground. The first diode is composed of a substrate of one of a P
−
-type and a P
−
on P
+
-type epitaxial type, and an N
+
-type region deposited on the substrate. Also, the first diode is further composed of a P
+
-type region deposited on the substrate and connected to the substrate ground, and a field oxidation film region formed to electrically insulate the N
+
-type region from the P
+
-type region. Also, the first diode is further composed of an N-type well surrounding the N
+
-type region to prevent avalanche from being generated in the first diode in response to an input voltage applied to the pad and lower than a predetermined voltage.
Also, a voice coil motor feedback control circuit is known in Japanese Laid Open Patent Application (JP-A-Heisei 8-163885 corresponding to U.S. patent application Ser. No. 08/300952). In this reference, the voice coil motor feedback control circuit is composed of an H bridge circuit (
10
), a controller (
20
) and a feed back loop (
60
). The feed back loop (
60
) prevents the voltage applied to the voice coil motor from increasing due to counter-electromotive force.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a transistor protecting circuit.
Another object of the present invention is to provide a transistor protecting circuit which can prevents an erroneous operation of a transistor and the destruction of the transistor.
Still another object of the present invention is to provides a transistor protecting circuit which can prevent through current from flowing between a power supply and the ground.
Yet still another object of the present invention is to provide a transistor protecting circuit in which the current drive ability to a gate of a transistor is enhanced.
It is another object of the present invention is to provide a transistor protecting circuit which is provided with an inverter, an RS latch, and an enhancing transistor.
In order to achieve an aspect of the present invention, a transistor protecting circuit for an H bridge circuit includes first to fourth buffers, and an enhancing circuit. The H bridge circuit includes a first P-channel transistor and a first N-channel transistor provided between a first power supply and a ground to be connected in series through a first node, and a second P-channel transistor and a second N-channel transistor provided between the first power supply and the ground to be connected in series through a second node. A load is connected between the first node and the second node. The first buffer inverts a first control signal to a first gate signal which is supplied to a gate of the first P-channel transistor via a first line, and the second buffer inverts a second control signal to a second gate signal which is supplied to a gate of the first N-channel transistor via a second line. Also, the third buffer inverts a third control signal a third gate signal which is supplied to a gate of the second P-channel transistor via a third line, and the fourth buffer inverts a fourth control signal to a fourth gate signal which is supplied supply to a gate of the second N-channel transistor via a fourth line. The third and fourth co
Han Jessica
Tibbits Pia
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