Transistor overload protection assembly and method with time-var

Details Transistor overload protection assembly and method with time-var Transistor overload protection assembly and method with time-var

1997-01-23

1998-09-15

Wong, Peter S.

Electricity: power supply or regulation systems

Output level responsive

Using a three or more terminal semiconductive device as the...

323284, G05F 1565, H02H 720

Patent

active

058084576

ABSTRACT:
An overload protection assembly and method for overload protection of a transistor includes a switching transistor connected between a load at a first terminal and a power source at a second terminal. A measuring circuit measures the voltage levels at the first and second terminals. The first terminal is measured before and after the measurement of the second terminal, and averaged to produce its voltage level. The measured voltage levels from the first and second terminals are subtracted from one another and the difference compared to preset limits to determine overload conditions. If overload conditions exist, the measuring circuit turns off the transistor.

REFERENCES:
patent: 3855520 (1974-12-01), Stich
patent: 3946280 (1976-03-01), Quist
patent: 4378580 (1983-03-01), Stich
patent: 4752864 (1988-06-01), Clappier
patent: 5448155 (1995-09-01), Jutras

Affiliated with

Also associated with

Rating

Transistor overload protection assembly and method with time-var does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Transistor overload protection assembly and method with time-var, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Transistor overload protection assembly and method with time-var will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-92096