Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control
Reexamination Certificate
1998-12-29
2001-06-19
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Amplitude control
C327S387000, C327S281000
Reexamination Certificate
active
06249169
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to an output circuit used in circuits such as a level converter circuit, logic circuit, and an operational amplifier circuit, and, more particularly, to an output circuit for outputting an output signal having an amplitude that exceeds the breakdown voltage of a transistor of the output circuit.
In the past, an output circuit equipped with a CMOS inverter circuit was driven by receiving power from a high potential power supply Vdd (for example, 5 volts) and a low potential power supply Vss (for example, 0 volts). An input signal is amplified in a full scale within the range of power supply Vdd or Vss levels. An inverse signal of the input signal is output from the output terminal of the inverter circuit.
Due to miniaturization of semiconductor integrated circuit devices in recent years, MOS transistors with a lower breakdown voltage than the power supply Vdd or Vss level are used. However, it is desirable to provide an output signal amplified in a full scale within the range of power supply Vdd or Vss level. Accordingly, the MOS transistor of the output circuit should have a breakdown voltage that exceeds the differential voltage between the power supplies Vdd and Vss. For this purpose, special MOS transistors with a high breakdown voltage are used for the output circuit. Specifically, the high breakdown voltage MOS transistor has a relatively thick gate insulating film formed by repeating a gate oxide film formation process during fabrication.
However, repeating the gate oxide formation process increases the dispersion of MOS transistor characteristics and raises the manufacturing costs of the devices. Moreover, because the MOS transistor with a thickly filmed gate insulating film has a relatively high threshold, it also has an increased on resistance. Consequently, the drive capacity of the transistor is decreased. In order to increase the drive capacity of the transistor, the size of the transistor can be increased. However, increasing the transistor size prevents high integration of semiconductor integration circuit devices.
It is an object of the present invention to provide an output circuit that outputs an output signal having an amplitude exceeding the breakdown voltage of the MOS transistors from which it is constructed.
SUMMARY OF THE INVENTION
In one aspect of the invention, an output circuit includes a PMOS transistor and an NMOS transistor connected in series. A potential control circuit is connected to the gate and source of the PMOS transistor and the NMOS transistor. The potential control circuit receives power from a high potential power supply and a low potential power supply, and controls the voltage applied to the gate and the source of the PMOS transistor and the NMOS transistor in response to an input signal having one of first level and a second level. The potential control circuit applies a reference voltage to the gates of the PMOS transistor and the NMOS transistor. The reference voltage is between the high potential power supply level and the low potential power supply voltage level. The potential control circuit applies the high potential power supply voltage to the source of the PMOS transistor in response to an input signal with the first level and applies a voltage to the source of the NMOS transistor to make the NMOS transistor nonconductive, so that an output signal with the high potential power supply voltage is output from a node between the PMOS transistor and NMOS transistor The potential control circuit applies the low potential power supply voltage to the source of the NMOS transistor in response to an input signal having the second level and apples a voltage to the source of the PMOS transistor to make the PMOS transistor nonconductive, so that an output signal having the low potential power supply voltage is output from the node between the PMOS transistor and NMOS transistor.
In another aspect of the invention, an output circuit includes a PMOS transistor and an NMOS transistor connected in series. A first source follower circuit is connected between the source of the PMOS transistor and a high potential power supply. The first source follower circuit selectively applies a high potential power supply voltage to the source of the PMOS transistor in response to a first input signal having a voltage that changes between the high potential power supply voltage and a reference voltage. The reference voltage is between the high potential power supply voltage and a low potential power supply voltage A second source follower circuit is connected between the source of the NMOS transistor and a low potential power supply. The second source follower circuit selectively applis the low potential power supply voltage to the source of the NMOS transistor in response to a second input signal having a voltage that changes between the reference voltage and low potential power supply voltage. An output terminal is located at a node between the PMOS transistor and the NMOS transistor. The output terminal outputs an output signal having one of the high potential power supply voltage and the low potential power supply voltage.
In yet another aspect of the invention, an output circuit includes a PMOS transistor and a NMOS transistor connected in series. A first inverter circuit is connected to the source of the PMOS transistor. The first inverter circuit receives power from a high potential power supply and a reference voltage between the high potential power supply voltage and a low potential power supply voltage. The first inverter receives a first input signal having a voltage that changes between the high potential power supply voltage and the reference voltage and apples one of the high potential power supply voltage and reference voltage to the source of the PMOS transistor. A second inverter circuit is connected to the source of the NMOS transistor. The second inverter circuit receives power from the reference voltage and a low potential power supply. The second inverter circuit receives a second input signal having a voltage that changes between the reference voltage and the low power supply voltage and applies one of the reference voltage and the low potential power supply voltage to the source of the NMOS transistor. An output terminal is located at a node between the PMOS transistor and the NMOS transistor. The output terminal outputs an output signal having one of the high potential power supply voltage and the low potential power supply voltage.
In one aspect of the invention, a level converter circuit includes an input signal converter for receiving power from a high potential power supply and a low potential power supply and converting an external input signal to first and second input signals. The first input signal has a voltage that changes between the high potential power supply voltage and a reference voltage. The reference voltage is between the high potential power supply voltage and the low potential power supply voltage. The second input signal has a voltage that changes between the reference voltage and the low potential power supply voltage. An output circuit is connected to the input signal converter. The output circuit receives the first and second input signals and outputs an output signal having one of the high potential power supply voltage and the low potential power supply voltage.
In another aspect of the invention, a logic circuit includes first and second power supplies for shifting voltages of first and second input signals, thereby generating first and second shifted input signals. An output circuit is connected to the first and second power supplies. The output circuit receives the first and second input signals and the first and second shifted input signals and outputs a predetermined logical signal. The output circuit includes a PMOS transistor and a NMOS transistor connected in series. A first NAND circuit is connected to the source of the PMOS transistor and receives power from the high potential power supply and a reference voltage. The reference
Armstrong Westerman Hattori McLeland & Naughton LLP
Fujitsu Limited
Lam Tuan T.
Nguyen Hiep
LandOfFree
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