Transistor manufacturing process using three-step base doping

Details Transistor manufacturing process using three-step base doping Transistor manufacturing process using three-step base doping

1989-11-20

1991-04-09

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 32, 437 56, 437 57, 437162, 437 63, 437917, 148DIG9, 148DIG124, H01L 21265

Patent

active

050064762

ABSTRACT:
In a transistor fabrication process, the use of a three-step base doping technique enables the characteristics of a vertical bipolar transistor to be controllably reproduced at highly optimal values from run to run. Insulating spacers (52A) are employed in forming a self-aligned base contact zone (58B). A shallow emitter (46) is created by outdiffusion from a patterned non-monocrystalline semiconductor layer (38A) that serves as the emitter contact. The fabrication process is compatible with the largely simultaneous manufacture of an insulated-gate field-effect transistor of the lightly doped drain type.

REFERENCES:
patent: 4539744 (1985-09-01), Burton
patent: 4587718 (1986-05-01), Haken et al.
Chen et al., "An Advanced Bipolar Transistor with Self-Aligned Ion-Implanted Base and W/Poly Emitter", IEEE Trans. Elec. Devs., vol. 35, No. 8, 8/88, pp. 1322-1327.
Cole, "Is BiCMOS The Next Technology Driver?", Electronics, Feb. 4, 1988, pp. 55-57.
Alverez et al., "2 Micron Merged Bipolar-CMOS Technology", IEDM Tech. Dig., Dec. 9-12, 1984, pp. 761-764.
Cuthbertson et al., "Self-Aligned Transistor with Polysilicon Emitters for Bipolar VLSI", IEEE Trans. Elec. Devs., Feb. 1985, pp. 242-247.
Konaka et al., "A 20 ps/G. Si Bipolar IC Using Advanced SST with Collector Ion Implantation," Extended Abs., 19th Conf. Solid State Devs. & Mats., 1987, pp. 331-334.

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