Transistor logic tristate device with reduced output capacitance

Details Transistor logic tristate device with reduced output capacitance Transistor logic tristate device with reduced output capacitance

1979-07-18

1982-01-19

Zazworsky, John

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307456, H03K 19088

Patent

active

043119271

ABSTRACT:
A transistor logic tristate output gate or device is provided with active or passive element arrangements coupled between the enable gate on the one hand and the base of the pull down element transistor on the other hand. This coupling affords a low impedance route to ground or low potential from the base of the pull down element when the enable gate is at low potential and the output device is in the high impedance third state. Miller feedback current at the base of the pull down element transistor is thereby diverted to ground. The coupling arrangement affords high impedance to current flow in the opposite direction thereby blocking current flow from the enable gate when the enable gate is at high potential. For active discharge of Miller current three transistors are provided in a double inversion series coupling between the enable gate and pull down element. Alternately a multiple emitter junction transistor is used. For passive element discharge of Miller current a low forward impedance high backward impedance large surface area diode is used.

REFERENCES:
patent: 3602733 (1971-08-01), Aoki
patent: 4081695 (1978-03-01), Allen et al.
patent: 4132906 (1979-01-01), Allen

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