Transistor layout for standard cell with optimized...

Details Transistor layout for standard cell with optimized... Transistor layout for standard cell with optimized...

2008-01-22

2008-01-22

Soward, Ida M. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

C257S203000, C257S204000, C257S205000, C257S206000, C257S207000, C257S208000, C257S209000, C257S210000, C257S211000, C257S401000

Reexamination Certificate

active

07321139

ABSTRACT:
A layout for a transistor in a standard cell is disclosed. The layout for a transistor includes an active region with at least one portion having a first edge and at least one portion having a second edge all perpendicular to a channel of the transistor; and a gate placed on top of the active region with a distance from an edge of the gate to the first edge being shorter than a distance from the edge of the gate to the second edge of the active region, wherein the active region is of a non-rectangular shape.

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