Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Isolation by pn junction only
Reexamination Certificate
2000-06-29
2002-06-18
Loke, Steven (Department: 2811)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Isolation by pn junction only
C438S216000, C438S222000, C438S223000, C438S261000, C438S287000, C438S300000, C438S303000, C438S416000, C438S418000, C438S564000, C438S591000, C438S595000, C438S589000, C438S522000, C438S607000, C257S213000, C257S325000, C257S329000, C257S336000, C257S344000, C257S346000, C257S350000, C257S382000, C257S384000, C257S386000, C257S408000, C257S591000, C257S595000
Reexamination Certificate
active
06406973
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to a transistor in a semiconductor device and method of manufacturing the same, and more particularly to, a transistor in a semiconductor device in which channels are formed in an elevated channel structure of Si/SiGe/Si and a buried/elevated SiGe layer is formed at the junction thereof, thus improving the electric characteristic of the transistor, and method of manufacturing the same.
2. Description of the Prior Art
Generally, as the semiconductor device becomes higher integrated, miniaturized and speeder, transistors having an improved short channel effect (SCE) capability, an improved hot carrier suppression (HCS) capability and an improved current driving force are required.
FIGS. 1A through 1D
are sectional views of a device for explaining a conventional method of manufacturing a transistor in a semiconductor device.
Referring now to
FIG. 1A
, a device separation film
12
is formed at a silicon substrate
11
to define an active region and a field region. Then, a N-well
13
is formed in order to form a PMOS transistor. After ion implantation process for controlling the threshold voltage is performed, a gate oxide film
14
and a gate electrode
15
are sequentially formed.
Referring to
FIG. 1B
, a gate spacer
16
is formed on both sides of the gate oxide film
14
and the gate electrode
15
. Next, a junction
17
is formed by ion implantation for formation of source/drain and for gate doping.
Referring to
FIG. 1C
, a Ti layer
18
is deposited on the entire structure. Then, the Ti layer
18
is processed by first annealing process, thus forming a TiSi
2
layer
18
a
on the junction
17
and the gate electrode
15
portions, in which silicon is exposed.
Referring to
FIG. 1D
, a portion of the Ti layer
18
not reacted by the first annealing process is removed by wet etching process and is then processed by second annealing process, thus forming a TiSi
2
layer
18
a.
As described above, the manufacturing of a transistor by the surface channel PMOS Ti-salicide forming technology employing TiSi
2
results in a structure in which a TiSi
2
is made due to consumption of underlying silicon. This technology is very disadvantageous since the junction depth necessarily required is reduced as the device design rule is reduced. For example, in a device having the design rule of less than 0.13 &mgr;m, the junction depth is about 1000 Angstrom in case of a PMOS transistor. At this time, when Ti of about 300 Angstrom is deposited, loss of silicon about more than 200 Angstrom is required from the substrate surface. Thus, the device junction portion highly doped more than 1E20 ions/cm
2
is greatly damaged, thus significantly reducing the expected current driving force of the junction.
Meanwhile, in a SC-PMOS structure using an existing polysilicon, the gate poly depletion effect (PDE) is increased due to low boron activation, thus reducing the current driving force due to a weak gate electric field.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a transistor in a semiconductor device in which channels are formed in an elevated channel structure of Si/SiGe/Si and a buried/elevated SiGe layer is formed at the junction thereof, thus improving the electric characteristic of the transistor, and method of manufacturing the same.
In order to accomplish the above object, the method of manufacturing a transistor in a semiconductor device according to the present invention is characterized in that it comprises the steps of forming a device separation film on a silicon substrate and then forming a well; after performing a first cleaning process, sequentially forming a first Si layer, a SiGe layer and a second Si layer by selective epi-silicon growth process and then performing ion implantation process for controlling the threshold voltage; forming a gate oxide film on the surface of the second Si layer and then forming a gate polysilicon layer pattern on the gate oxide film; forming gate spacers on both sides of the gate polysilicon layer pattern and then etching the gate polysilicon layer pattern by wet silicon dipping process, thus forming a remaining gate polysilicon layer pattern; after performing a second cleaning process, performing a selective SiGe growth process to form an epi-SiGe layer and a poly-SiGe layer at the exposed portions of the SiGe layer and the remaining gate polysilicon layer pattern, respectively; and after performing ion implantation process for source/drain formation and gate doping, depositing a Ti layer on the entire structure, removing the Ti layer that was not reacted after a first annealing process and then forming a TiSi
2
layer on the exposed portion of the epi-SiGe layer and the poly-SiGe layer by a second annealing process, thus completing a gate electrode, an elevated channel and a buried/elevated junction.
Also, in order to accomplish the above object, the transistor in a semiconductor device according to the present invention is characterized in that it comprises a silicon substrate in which a device separation film and a well are formed; an elevated channel in which a first Si layer, a SiGe layer and a second Si layer are stacked on some of the silicon substrate; a gate electrode in which a polysilicon layer, a poly-SiGe layer and a TiSi
2
layer are stacked on the channel, electrically separated from the channel by the gate oxide film; and a buried/elevated junction in which a first Si layer, a SiGe layer, an epi-SiGe layer and a TiSi
2
layer are stacked on both sides of the gate electrode, electrically separated from the gate electrode by a gate spacer.
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Hyundai Electronics Industries Co,. Ltd.
Kang Donghee
Loke Steven
Pennie & Edmonds
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