Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Amorphous semiconductor material
Reexamination Certificate
2002-09-13
2004-05-18
Abraham, Fetsum (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Amorphous semiconductor material
C257S059000, C257S065000, C257S066000, C257S200000, C257S347000
Reexamination Certificate
active
06737673
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device including a circuit constituted of bottom gate type thin film transistors (hereinafter abbreviated as TFT) formed by using a semiconductor thin film. Particularly, the present invention relates to a semiconductor device using inverted stagger type TFTs.
Incidentally, in the present specification, the semiconductor device means a device capable of functioning with semiconductor characteristics, and includes not only a single component such as a TFT but also a semiconductor circuit, an electro-optical device, and an electronic equipment incorporating the circuit or device as a part.
2. Description of the Related Art
In recent years, a semiconductor device has attracted attention, in which TFTs are formed on a substrate by using a semiconductor thin film having crystallinity and a circuit is constituted of the TFTs. Although polycrystal silicon (also called polysilicon) is most popular for a semiconductor thin film, researches for using a compound semiconductor expressed by Si
X
Ge
1−X
(0<X<1) has also been carried out.
Although a TFT using a polysilicon film has reached the stage of practical use, there is much room for development in improvement of film quality and mass productivity, and further technical development is needed. In such circumstances, Japanese Patent Laid-Open No. Hei. 7-130652, the disclosure of which is herein is incorporated by reference, by the present applicant discloses a technique as means for solving the problems of the improvement of film quality of polysilicon and the improvement of mass productivity at the same time.
The technique disclosed in the publication is such that a catalytic element for facilitating crystallization of silicon is added to an amorphous semiconductor film (typically amorphous silicon) so that crystallization is made by using the function thereof. As a result, temperature and time necessary for crystallization was lowered and throughput was remarkably improved. Further, it was ascertained that obtained polysilicon had extremely high crystallinity and electrical characteristics of a TFT was greatly improved.
However, since nickel (Ni) that is most effective as the catalytic element is a metal element, there is a fear that if nickel remains in polysilicon, it has a bad influence on TFT characteristics. Thus, the present applicant has considered that it is necessary to remove surplus nickel after completion of crystallization, and has developed a technique for carrying out gettering of the catalytic element (Japanese Patent Laid-open No. Hei. 9-312260, the disclosure of which is herein incorporated by reference).
In both of the techniques set forth in these publications, the point is to use a metal element, such as nickel, as a catalytic element for facilitating crystallization. The catalytic element itself becomes unnecessary after polysilicon is obtained.
SUMMARY OF THE INVENTION
The present invention has been made in view of the above problems, and an object thereof is to provide a technique for forming a semiconductor thin film with high crystallinity by a manufacturing method having high productivity. Another object is to make improvement in a manufacturing yield and manufacturing cost of a semiconductor device by constructing a circuit with TFTs using such a semiconductor thin film.
According to the present invention, germanium (Ge) of semiconductor is used as a catalytic element for facilitating crystallization of silicon, so that a process which does not require gettering is provided. Since germanium has properties which are very close to those of silicon, it exists in silicon in the good state of conformity. That is, germanium has a merit that even if it is not particularly removed after the use as a catalytic element, it does not have a bad influence on TFT characteristics.
Basically, germanium is added to an amorphous silicon film, and the amorphous silicon film is crystallized by using the catalytic function of germanium. By this, lowering of temperature at crystallization, lowering of a process time, and shortening of steps can be realized at the same time.
Since germanium exists in silicon in the state with extremely excellent conformity, as compared with cases of using other catalytic elements, crystallinity is very high. Since germanium continuously changes the bandgap of silicon according to its content, it is possible to form an active layer with a bandgap narrower than polysilicon. By using such an active layer for a TFT, a mobility (field effect mobility) higher than that of a TFT using an active layer of polysilicon can be realized.
REFERENCES:
patent: 4971832 (1990-11-01), Arai et al.
patent: 5241214 (1993-08-01), Herbots et al.
patent: 5414547 (1995-05-01), Matsuo et al.
patent: 5424244 (1995-06-01), Zhang et al.
patent: 5461250 (1995-10-01), Burghartz et al.
patent: 5478780 (1995-12-01), Koerner et al.
patent: 5643826 (1997-07-01), Ohtani et al.
patent: 5700333 (1997-12-01), Yamazaki et al.
patent: 5808321 (1998-09-01), Mitanaga et al.
patent: 5830784 (1998-11-01), Zhang et al.
patent: 5859443 (1999-01-01), Yamazaki et al.
patent: 5897347 (1999-04-01), Yamazaki et al.
patent: 5915174 (1999-06-01), Yamazaki et al.
patent: 5923997 (1999-07-01), Mitanaga et al.
patent: 5932892 (1999-08-01), Hscuh et al.
patent: 5932893 (1999-08-01), Miyanaga et al.
patent: 5937282 (1999-08-01), Nakajima et al.
patent: 5953597 (1999-09-01), Kusumoto et al.
patent: 5961743 (1999-10-01), Yamazaki et al.
patent: 5962871 (1999-10-01), Zhang et al.
patent: 5977559 (1999-11-01), Zhang et al.
patent: 5985740 (1999-11-01), Yamazaki et al.
patent: 6037635 (2000-03-01), Yamazaki
patent: 6049110 (2000-04-01), Koh
patent: 6122025 (2000-09-01), Kim
patent: 6201585 (2001-03-01), Takano et al.
patent: 6246070 (2001-06-01), Yamazaki et al.
patent: 6410961 (2002-06-01), Hayashi
patent: 2001/0019154 (2001-09-01), Yamazaki et al.
patent: 7-130652 (1995-05-01), None
patent: 9-312260 (1997-12-01), None
Subramanian et al., A Novel Technique for 3-D Integration: Ge-seeded Laterally Crystallized TFTs, Digest of Technical Papers: 1997 Symposium on VLSI Technology, Jun. 10-12, 1997, pp. 97-98.
James W. Mayer, “Electronic Material Science for Integrated Circuits in Si and GaAs,” Macmillan Publishing Company, New York, 1990, pp. 176-179.
Abraham Fetsum
Robinson Eric J.
Robinson Intellectual Property Law Office P.C.
Semiconductor Energy Laboratory Co,. Ltd.
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