Transistor having multiple channels

Details Transistor having multiple channels Transistor having multiple channels

2006-09-26

2006-09-26

Huynh, Andy (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Junction field effect transistor

C257S241000, C257S328000, C257SE29131, C257SE21693

Reexamination Certificate

active

07112832

ABSTRACT:
A transistor (10) overlies a substrate (12) and has a plurality of overlying channels (72, 74, 76) that are formed in a stacked arrangement. A continuous gate (60) material surrounds each of the channels. Each of the channels is coupled to source and drain electrodes (S/D) to provide increased channel surface area in a same area that a single channel structure is conventionally implemented. A vertical channel dimension between two regions of the gate (60) are controlled by a growth process as opposed to lithographical or spacer formation techniques. The gate is adjacent all sides of the multiple overlying channels. Each channel is formed by growth from a common seed layer and the source and drain electrodes and the channels are formed of a substantially homogenous crystal lattice.

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International Search Report.
Specification, abstract and drawings for U.S. Appl. No. 10/074,732, filed Feb. 13, 2002.

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