Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – Having specific type of active device
Reexamination Certificate
1997-02-26
2001-03-06
Loke, Steven H. (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
Having specific type of active device
C257S401000, C257S526000, C257S786000
Reexamination Certificate
active
06198117
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and, more particularly, to a transistor of a master-slice type applied to use in high or radio frequency (RF).
In order to realize an RF bipolar transistor in a master-slice type IC, such a method has been conventionally employed that a plurality of transistor cells having different numbers of emitter electrodes (hereinafter referred to as “a finger number”) are arranged in one semiconductor chip, and those transistor cells having required finger number among them are used or adjacent transistor cells having different finger number are combined in use.
This method will be explained in more detail with reference to
FIG. 7
to FIG.
9
. Here, FIG.
7
and
FIG. 8
show plan views of semiconductor chips of conventional semiconductors formed according to master slice approach, and
FIG. 9
shows plan views when this semiconductor chip is connected to lead wires of a lead frame.
As shown in FIG.
7
(
a
), a first transistor cell
102
, a second transistor cell
103
and a third transistor cell
104
are formed in predetermined respective regions of a semiconductor chip
101
. Although not shown, these transistor cells
102
-
104
are bipolar transistors having an emitter, a base and a collector, respectively, and the finger numbers of these transistors are different from one another. Namely, those transistors
102
-
104
are formed so as to have different size from one another. Note that slanting lines are shown in these transistor cells for the purpose of clarifying the arrangement in the semiconductor chip.
In such a semiconductor chip in which transistor cells
102
-
104
are arranged, a plural sorts of transistors are manufactured by varying the number of used transistor cells and the electrode configurations as shown in FIG.
7
(
b
), FIG.
7
(
c
), or FIG.
8
(
a
), FIG.
8
(
b
) and so on conforming to RF characteristics and current values fitting the use purpose.
In one configuration as shown in FIG.
7
(
b
), bonding pads
105
and
106
are connected to the first transistor cell
102
through interconnection lines, respectively. Here, the bonding pad
105
is connected to the emitter of the first transistor cell
102
and the bonding pad
106
is connected to the base of the first transistor cell
102
. An electrode of the collector is drawn out of the back of the semiconductor chip
101
.
In another configuration as shown in FIG.
7
(
c
), bonding pads
107
and
108
are connected to the first transistor cell
102
and the second transistor cell
103
through interconnection lines, respectively. The bonding pad
107
is connected in common to the emitters of the first transistor cell
102
and the second transistor cell
103
, and the bonding pad
108
is connected in common to the bases of the first transistor cell
102
and the second transistor cell
103
. The electrode of the collector is also drawn out of the back of the semiconductor chip
101
.
In a still another configuration as shown in FIG.
8
(
a
), bonding pads
109
and
110
that are common to the first transistor cell
102
, the second transistor cell
103
and the third transistor cell
104
are formed in a similar manner. The bonding pad
109
serves as an emitter electrode, and the bonding pad
110
serves as a base electrode. The collector electrode is also provide on the back side of the semiconductor chip
101
.
FIG.
8
(
b
) shows a case in which two bonding pads
111
and
112
are connected to the same emitter. Namely, bonding pads
111
and
112
are connected to the emitters of the first transistor cell
102
and the second transistor cell
103
through interconnections. Further, a bonding pad
113
is connected to the bases of the first transistor cell
102
and the second transistor cell
103
through interconnections. The electrode of the collector is also drawn out of the back of the semiconductor chip
101
.
Thus, in the above approach, the positions of the respective bonding pads are different from one another depending on the sort of products.
In an assembly, as shown in FIG.
9
(
a
) applied to the semiconductor chip of FIG.
7
(
b
), the bonding pad
105
of the semiconductor chip
101
is connected to an external emitter lead
115
by a bonding wire
114
, and the bonding pad
106
is connected to an external base lead
117
by a bonding wire
116
. The semiconductor chip
101
is mounted on a collector lead
118
. On the other hand, in the device as shown in FIG.
9
(
b
) applied to the chip of FIG.
8
(
a
), the bonding pad
109
of the semiconductor chip
101
is connected to the emitter lead
115
by a bonding wire
119
, and the bonding pad
110
is connected to the base lead
117
by a bonding wire
120
.
Thus, the lead frame as shown in
FIG. 9
can be used for the chips shown in FIGS.
7
(
b
) and
8
(
a
). However, this lead frame is not applicable to the chip shown in FIG.
8
(
b
). This is because, two wires from the pads
111
and
112
are so close to each other that a bonder cannot perform an bonding operation.
Further, in the above approach, the position of the bonding pad varies every time the sort is different, i.e., every time the number of transistors used and the combination thereof are varied. As described in FIG.
9
(
a
) and FIG.
9
(
b
), it is comprehended that the bonding pad position becomes different case by case. Namely, there has been such a problem that positioning of bonders becomes necessary every time the assembled products are switched over one another at time of bonding, thus lowering assembly efficiency. Further, no influence is exerted upon RF characteristics when a transistor is used in a low frequency band since one wavelength of the used frequency is long. When it is used in a high frequency band in giga-cycle order such as an L band (1 to 2 giga-Hz band), however, when the distance of drawing out the electrode up to the bonding pads of respective transistor cells is different, a plurality of RF waves having different phases are applied to bonding pads where output is produced, which has caused lowering of power gain or deterioration of frequency characteristics of a transistor sometimes. Further, since the bonding wire length is different for every assembly product, when device parameters required when a module using these transistors or the like is designed are extracted, it has been required to extract the device parameters for every sort at transistor portions and other portions than those portions, thus showing poor design efficiency. Furthermore, when the electrode drawing out configuration differs between either side, the impedance and parasitic capacity values for respective transistors become different. In addition, calorific values at time of operations are different and junction temperatures become different by the different among respective transistor sizes. Thus, there has been such a problem that base to emitter voltage becomes different for every transistor cell and the operating point of the transistor as a semiconductor chip is shifted, thus causing lowering of a power gain and deterioration of frequency characteristics.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide an improved semiconductor device of a master slice type adoptable to use in RF range.
A semiconductor device according to one aspect of the present invention is provided as a transistor formed in a master slice manner, in which a transistor that shows the smallest scale among a product group of transistors manufactured according to master slice approach is arranged at the central part of the semiconductor chip as a principal transistor cell, and sub-transistor cells are arranged at positions that are symmetrical on the semiconductor chip putting the principal transistor cells therebetween.
It is convenient that a plurality of bonding pads are arranged on left and right in symmetrically with respect to the center line of the semiconductor chip.
With the above construction, the symmetric property of arrangement on a semiconductor chip of such
Loke Steven H.
NEC Corporation
Sughrue Mion Zinn Macpeak & Seas, PLLC
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