Transistor gate shape metrology using multiple data sources

Details Transistor gate shape metrology using multiple data sources Transistor gate shape metrology using multiple data sources

2008-05-13

2008-05-13

Picard, Leo (Department: 2125)

Data processing: generic control systems or specific application

Specific application, apparatus or process

Product assembly or manufacturing

C700S029000

Reexamination Certificate

active

11469206

ABSTRACT:
The claimed subject matter can provide a mechanism for ascertaining a variety of metrological data relating to one or more features (e.g., a transistor gate) of a chip/wafer. In addition, results of electrical testing on the chip/wafer can also be gathered and, together with the metrological data, input to a data store. From the information in the data store, a three-dimensional model for the feature(s) of the chip/wafer can be constructed and subjected to analysis, testing, and/or simulation. As well, the three-dimensional model can be optimized and an optimized three-dimensional model can be employed to affect process control in a feedback/forward manner, e.g., to apply optimizations to the next or the current wafer, respectively. Accordingly, the disclosed mechanisms may be used to optimize semiconductor performance, yield, or for research and development. In addition the three-dimensional model may be used in analysis, simulation, or debugging software.

REFERENCES:
patent: 5621652 (1997-04-01), Eakin
patent: 6978229 (2005-12-01), Saxena et al.
patent: 6988017 (2006-01-01), Pasadyn et al.
patent: 7085676 (2006-08-01), Opsal et al.
patent: 2004/0181768 (2004-09-01), Krukar
patent: 2005/0057748 (2005-03-01), Vuong et al.
patent: 2005/0192914 (2005-09-01), Drege et al.
patent: 2005/0216109 (2005-09-01), Radigan et al.
patent: 2006/0187466 (2006-08-01), Li et al.
patent: 2007/0026321 (2007-02-01), Kumar
Opsal et al. “Real-time Opticla CD Metrology for Litho Process”, 2003, Proceedings of SPIE, vol. 5038 pp. 496-507.
Gorelikov et al.,“CD-SEM-based Critical Shape Metrology of Integrated Circuits”, Proceedings of SPIE, 2004,pp. 1-10.
Arisha et al., “A simulation model to characterize the photolithography process of a semiconductor wafer fabrication”, 2004, Elsevier, pp. 2071-2079.
Stoddard et al.; “Application of Feed-Frpward and Adaptive Feedback Control to Semiconductor Device Manufacturing”; Jun. 1994; Proceedings of the American Control conference; pp. 892-896.

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