Transistor fabrication methods using reduced width sidewall...

Details Transistor fabrication methods using reduced width sidewall... Transistor fabrication methods using reduced width sidewall...

2006-03-14

2006-03-14

Nhu, David (Department: 2818)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S680000

Reexamination Certificate

active

07012028

ABSTRACT:
Transistor fabrication methods (50) are presented in which shrinkable sidewall spacers (120) are formed (66, 68) along sides of a transistor gate (114), and a source/drain implant is performed (74) after forming the sidewall spacer (120). The sidewall spacer width is then reduced by annealing the shrinkable sidewall spacer material (76) following the source/drain implant (74).

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