Transistor fabrication method

Details Transistor fabrication method Transistor fabrication method

1990-06-26

1991-09-03

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 40, 437 29, 437913, H01L 21265

Patent

active

050454862

ABSTRACT:
A method of forming a transistor is disclosed. Conventional fabrication techniques direct an ion implantation beam toward a substrate upon which a gate has already been formed. If the gate stack is too low relative to the incident beam energy, the dopant species may channel thorugh the gate stack, adversely affecting transistor performance. The present invention prevents channeling through this gate by covering the gate with a protective layer before ion implantation.

REFERENCES:
patent: 4382827 (1983-05-01), Romano-Moran et al.
patent: 4616399 (1986-10-01), Ooka
patent: 4728617 (1988-03-01), Woo et al.
patent: 4818714 (1989-04-01), Haskell
patent: 4874713 (1989-10-01), Gioia
"Channeling of Implanted Phosphorus Through Polycrystalline Silicon," T. E. Seidel, Appl. Phys. Lett. vol. 36, No. 6, Mar. 15, 1980, pp. 447-449.
"Arsenic Ion Channeling Through Single Crystal Silicon," Y. Wada et al., J. Electrochem. Soc.: Solid-State Science and Technology, Jan. 1980, pp. 206-210.

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