Transistor device testing employing virtual device fixturing

Details Transistor device testing employing virtual device fixturing Transistor device testing employing virtual device fixturing

2000-12-26

2003-04-01

Cuneo, Kamand (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S762010, C324S762010

Reexamination Certificate

active

06541993

ABSTRACT:

FIELD OF THE INVENTION
The field of the present invention relates generally to testing transistor devices and, more specifically, to methods and apparatus employing “virtual” impedance fixturing for testing transistor devices.
BACKGROUND
A typical radio frequency (RF) power amplifier is constructed by paralleling several transistors together to achieve higher output power than is possible from a single transistor.
FIG. 1
depicts a power amplifier circuit using parallel transistors, as adapted from Gonzalez, Guillermo,
Microwave Transistor Amplifiers Analysis and Design,
Second Edition, Prentice Hall, 1997, p. 364. A signal source V
S
105
with source impedance Z
S
110
is connected to the parallel transistor device input
130
through an input impedance transformation network
115
. Similarly, a load impedance Z
L
145
is coupled to the parallel transistor device output
135
via an output impedance transformation network
125
. The gates of each transistor in the parallel transistor device are coupled together in a single input node
130
. Similarly, the drains of each transistor are coupled together to form a single output node
135
. Finally, the source of each transistor is coupled directly to ground
140
. An enlarged physical representation of a typical parallel transistor construction at the device level is depicted in
FIG. 2
, wherein the parallel transistors comprise a series of interleaved fingers that are formed in an interlocking configuration.
The methods employed to test a packaged power amplifier generally require that the power amplifier be mounted to a test fixture.
FIG. 3
represents a block diagram of a typical test fixture
300
used to house a device under test (“DUT”)
305
, while the DUT
305
undergoes testing by automated testing equipment (ATE). The DUT
305
is coupled at its input terminal by an input impedance transformation (or “matching”) network
310
. Similarly, the DUT is coupled at its output terminal by an output matching network
315
. The input and output matching networks
310
and
315
are often implemented using microstrip technology. However, many other designs for reducing the imaginary components of capacitance and inductance may be employed, including on-board discrete components like capacitors and inductors.
The inverse relationship between an extremely high power gain realizable by RF power amplifiers and the correspondingly low impedance levels required in order to achieve this gain is in large part responsible for the drawbacks from which the test fixture of
FIG. 3
suffers. For example, extremely low impedance devices make testing difficult. Modem automated testing equipment is designed on an impedance matching standard of 50 ohms, meaning that the input and output matching networks
310
and
315
of
FIG. 3
must match the input and output impedances of the DUT
305
to the 50-ohm impedance level of the test equipment. The input and output impedances of a typical packaged RF amplifier nominally ranges between one-half ohm and five ohms. Thus, testing power amplifier devices is troublesome largely due to the impedance transformation required to step the 50-ohm test equipment impedance down to the single-digit impedance level of the device. Further, the input and output matching networks
310
and
315
are application specific, requiring a separate and distinct test fixture for each type of device. Because the matching networks
310
and
315
of
FIG. 3
are physical components of the ATE, application independence also requires separate ATE for each device type.
Notably, in a high capacity manufacturing environment where multiple test stations are often employed, fixture cross-correlation must be maintained within tolerances to ensure that a device tested at one ATE station will produce the same results that the same device, or a nearly identical device, would produce if it were tested at a different ATE station. This maintenance of fixture cross-correlation is time consuming, inexact, and highly error-prone. Furthermore, modifications to microstrip impedance matching networks often involve an imprecise manipulation of board-level components, contributing to even greater fixture cross-correlation miscalibration.
SUMMARY OF THE INVENTION
The present invention is directed to “virtual” fixturing of a device being tested, the virtual fixturing being implemented by “de-embedding” the input and output matching networks of a physical test fixture.
In accordance with one aspect of the invention, a method for testing a transistor device is provided, comprising measuring small signal scatter parameters of the device, measuring a performance characteristic of the device, and transforming the measured performance characteristic based on the measured small signal scatter parameters of the device.
In accordance with another aspect of the invention, a system is provided for testing a transistor device, such as a laterally diffused metal oxide semiconductor (LDMOS) power transistor package. In a preferred embodiment, the system includes a test station having an input for coupling to a input terminal and an output for coupling to an output terminal, respectively, of the device, a network analyzer coupled to the test station for measuring small signal scatter parameters and for measuring a performance characteristic of the device, and a processor coupled to the network analyzer, the processor configured for transforming the measured performance characteristic based on the measured small signal scatter parameters.
An advantage of the invention is that a universal test fixture may be used for multiple types of devices to be tested, without having to change out the impedance matching networks at both ends of the device. Having a universal test fixture for multiple device applications eliminates errors associated with inter-fixture calibration from testing station to testing station within the manufacturing environment. Calibration of the virtual device fixture is performed in software and is consequently less cumbersome than the making board-level modifications otherwise required for impedance calibrations when preparing a test fixture for product testing.
Other and further aspects and advantages of the present invention will become apparent from the following detailed description and accompanying drawings.


REFERENCES:
patent: 5191294 (1993-03-01), Grace et al.
patent: 6397160 (2002-05-01), Craig et al.

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