Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor
Reexamination Certificate
2002-07-02
2004-12-21
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Junction field effect transistor
C257S256000, C257S279000, C257S280000
Reexamination Certificate
active
06833571
ABSTRACT:
BACKGROUND OF THE INVENTION
One way to increase the switching speed of a Field Effect Transistor (FET) and increase f
T
is to fabricate a standard transistor to be as small as possible. This methodology is generally known as microminiaturization, which has its limitations. For example, a difficulty associated with microminiaturization is the limitation of photolithography techniques in patterning nano-scale devices. The fabrication of the nano-scale devices using photolithography can result in a low yield because the devices are so small. However, when fabrication of a shorter channel FET is achieved, transit time in the channel beneath a gate becomes sufficiently short so that a switching speed, f
T,
of the transistor is consequently increased.
SUMMARY OF THE INVENTION
One aspect of the present invention is directed towards increasing operational speeds of transistor devices. In an illustrative embodiment, a transistor device includes a gate region disposed adjacent to a semiconductor substrate such that a low impedance channel is formed between a source region and drain region of a transistor device when a voltage is applied to its gate. The drain region of the device can be disposed aside the gate region on a common surface of the semiconductor substrate. The source region of the device also can be disposed adjacent to the substrate but on a side of the semiconductor substrate opposing the drain and/or gate regions. Based on this topology, a transistor device can be fabricated with a buried source to enhance its operating characteristics such as switching speed, gain, transconductance, etc.
A portion of the source region of the transistor device can be disposed directly opposite the gate region so that the semiconductor substrate is disposed between the gate and source regions. Consequently, a shorter distance can be achieved between the source and drain of the transistor device. Additionally, the gate region can be in contact with the channel (a semiconductor material) and cover a larger surface area than the source region. This aspect of the invention can vary depending on the application.
An insulation layer can be disposed adjacent to the semiconductor substrate opposite the gate region. For example, in one application, the semiconductor substrate is formed on an initially un-doped Silicon or Galium Arsenide substrate. The source region can be embedded within this non-conductive (or high impedance) layer, opposite the gate and drain of the transistor device. Based on this topology, the gate and/or source can be located on one side of the semiconductor substrate while the source can be disposed on another side of the semiconductor substrate or channel.
To support connections with other electronic devices, electrodes can be attached to the terminals of the transistor device. For example, an electrode can be electrically attached to the source region via an insulated conductor extending through the semiconductor substrate. Consequently, the gate, drain and source regions can be accessed from a common side of the transistor device. Alternatively, the source is accessed from a side of the semiconductor substrate opposite the drain.
The semiconductor substrate of the transistor device can be Gallium Arsenide. However, it should be noted that any suitable material can be used as a substrate.
The drain region can be disposed at an opposite end of the gate region with respect to the source region. Additionally, the drain region can be spaced from the gate region.
During operation, a voltage can be applied to the gate region to generate a depletion region deep enough in the semiconductor substrate so that a low impedance path is formed between the opposing drain and source regions.
Certain aspects of the present invention are advantageous over the prior art. For example, disposing a source opposite the drain region of a transistor device can shorten the path between the drain and source. As a consequence of shortening the travel path between the source and drain region, the transit time in the channel between gate decreases so that the switching speed of the device is thus increased.
Another aspect of the present invention is the enhanced electrical field profile afforded by disposing a source region beneath or opposing a gate region. More specifically, the average depth of a depletion region can be enlarged so that an effective capacitance of the device is smaller. That is, the gate to source capacitance can be reduced to increase its turn-on and turn-off time.
Faster switching transistor devices can be used to produce higher speed analog and digital electronic circuits. For instance, the speed of processor or amplifier circuits can be increased using the transistor devices according to certain principles of the present invention. The gain of a transistor can also be modified or enhanced.
Yet another aspect of the present invention, e.g., buried source, is that a transistor can occupy a much smaller area on a chip since the source is buried and the space between a corresponding source and gate can be eliminated. Therefor, an advantage of the novel device according to certain principles of the present invention is that a smaller device can be fabricated without necessarily changing corresponding resolution of the photolithography masks. Based on the new feature of burying the source beneath the gate, a conventional set of masks previously used to manufacture conventional transistor devices can be modified to form a transistor device according to certain principles of the present invention. For example, one change in fabrication procedure can involve connecting the source through a second layer of metalization. In a conventional MESFET device as in the prior art, the source is connected at the top metalization layer along with a corresponding gate and source.
REFERENCES:
patent: 3825996 (1974-07-01), Barron et al.
patent: 4222063 (1980-09-01), Rodgers
patent: 4679298 (1987-07-01), Zuleeg et al.
patent: 4737469 (1988-04-01), Stevens
patent: 5068705 (1991-11-01), Tran
patent: 5448085 (1995-09-01), Calcatera et al.
patent: 6184555 (2001-02-01), Tihanyi et al.
Lee et al, “Self-Aligned Gate MESFET and the Method of Fabricating the Same”, US Statutory Invention Registration, Reg. No. H390, Dece,ber 1, 1987.*
IBM Technical Disclosure Bulletin, “Planar Junction Gate Field Effect Transistor”, vol. 14, Issue 1, pp. 297 (TDB-ACC-NO: NN7106297); Jun. 1, 1971.*
IBM Technical Disclosure Bulletin, “Short Channel Vertical JFET Structure”, vol. 23, Issue 6, pp. 2567-2571 (TDB-ACC-NO: NN80112567); Nov. 1, 1980.
Gil Carlos A.
Mil'shtein Samson
Flynn Nathan J.
Hamilton Brook Smith & Reynolds P.C.
Mondt Johannes
University of Massachusetts Lowell
LandOfFree
Transistor device including buried source does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Transistor device including buried source, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Transistor device including buried source will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3338026