Transistor coupled logic circuit

Details Transistor coupled logic circuit Transistor coupled logic circuit

1974-12-23

1976-12-21

Zazworsky, John

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307215, 307218, 307300, 307315, 357 15, 357 40, 357 91, H03K 1908, H03K 1922, H03K 1936

Patent

active

039990800

ABSTRACT:
A TTL logic circuit employing single emitter PNP input transistors instead of a multi-emitter input stage, in order to reduce loading on input drive devices. The circuit features a logic swing of 1.6 volts centered on a circuit threshold of 1.6 volts with the logic 0 and logic 1 levels being internally clamped with p-n diode junctions to prevent transistor saturation and improve transistor switching speeds over those normally obtained using Schottky diode clamping techniques. The circuit output incorporates a Darlington stage and provides a logic 1 drive capability permitting the circuit to drive a terminated signal line having a low characteristic impedance, typically 50 ohms while maintaining a logic 1 level above 2.0 volts at 25.degree. C. Use of ion implantation techniques to define the isolation, emitter and base regions as well as the p-n diode junctions permits smaller device geometries and high F.sub.T transistors capable of high speed switching.

REFERENCES:
patent: 3217181 (1965-11-01), Zuk
patent: 3394268 (1968-07-01), Murphy
patent: 3515899 (1970-06-01), May
patent: 3544808 (1970-12-01), Mukai
patent: 3624620 (1971-11-01), Andrews

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