Transistor construction for low noise output driver

Details Transistor construction for low noise output driver Transistor construction for low noise output driver

1988-09-09

1990-08-14

Jackson, Jr., Jerome

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307579, 307594, 357 51, H01L 2978

Patent

active

049491393

ABSTRACT:
A transistor construction having a gate electrode meandering in a serpentine manner between interlacked comb-like drain and sources electrodes. The construction is equivalent to parallel transistors with series-connected gates, and the resistivity of the gate electrode forms a RC delay line in which transistors furthest from the gate drivers lag behind those which are closest. Accordingly, the transistor construction turns on or off gradually. The construction is useful as part of a CMOS output driver to memory chips and the like where the inductance of bondwires and the package leads normally cause noise spikes. The transistor construction reduces the current slew rate during switching so that less noise occurs on the chip supply lines. Another embodiment is made up of up to four parallel connected blocks of series-connected-gates. Multiple gate turn-off drivers are provided in a modified output driver, connected in parallel to each series-connected gate block, to insure that the transistor block turns off more rapidly than it turns on.

REFERENCES:
patent: 4725747 (1988-02-01), Stein et al.
patent: 4771195 (1988-09-01), Stein
patent: 4789793 (1988-12-01), Ehni et al.
Will C. H. Gubbels et al., "A 40 ns/100 pF Low-Power Full-CMOS 256K (32K.times.8) SRAM", IEEE Journal of Solid State Circuits, Oct. 1987, pp. 741-747.
George Canepa et al., "A 90 ns 4M6 CMOS EPROM", 1988 IEEE International Solid-State Circuits Conference, Feb. 1988, pp. 120-121.
Frans List et al., "A 25 ns Full-CMOS 1M6 SRAM", 1988 IEEE International Solid-State Circuits Conference, Feb. 1988, pp. 178-179.
Hsing-San Lee et al., "An Experimental 1M6 CMOS SRAM with configurable Organization and Operation", 1988 IEEE International Solid-State Circuits Conference, Feb. 1988, pp. 180-181.

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