Transistor circuit for signal multiplier

Details Transistor circuit for signal multiplier Transistor circuit for signal multiplier

1985-02-28

1987-09-15

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307529, 307498, 328160, H03B 1700, G06G 716

Patent

active

046942041

ABSTRACT:
A transistor circuit for a signal multiplier used in, for example, a demodulator by means of the Costas loop method is disclosed. The transistor circuit comprises first to third circuit stages each including first and second transistors coupled in a differential form. The first to third circuit stages are connected in tandem with one another such that the output signal current of each circuit stage is supplied to the succeeding circuit stage without a substantial change. Further, each of the first to third circuit stages is supplied with one of or both of two input signals P and Q. As a result, the transistor circuit produces an output signal representing a signal multiplication: P.times.Q.times.(P+Q).times.(P-Q).

REFERENCES:
patent: 3838262 (1974-09-01), vande Plassche
patent: 3956643 (1976-05-01), Hite
patent: 4308471 (1981-12-01), Misawa
patent: 4586155 (1986-04-01), Gilbert

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