Transistor base current error correction scheme for low...

Details Transistor base current error correction scheme for low... Transistor base current error correction scheme for low...

2000-10-11

2002-02-05

Pascal, Robert (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including current mirror amplifier

C323S315000

Reexamination Certificate

active

06344776

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates in general to electronic circuits, and is particularly directed to new and improved transistor circuit architecture for correcting for base current errors or offsets in a low voltage application such as, but not limited to the, coupling of a subscriber line interface circuit to a low voltage codec.
BACKGROUND OF THE INVENTION
Systems employed by telecommunication service providers contain what are known as subscriber line interface circuits or ‘SLIC’s, which interface communication signals with tip and ring leads of a wireline pair serving a relatively remote piece of subscriber communication equipment. In order to be interfaced with a variety of telecommunication circuits, including those providing codec functionality, present day SLICs must conform with a very demanding set of performance requirements, including accuracy, linearity, insensitivity to common mode signals, low noise, low power consumption, filtering, and ease of impedance matching programmability.
Indeed, as designers of integrated circuits employed for digital communications, such as codecs and the like, continue to ‘lower the voltage supply rail bar’ requirements for their devices (e.g., from five volts down to three volts), through the use of differential voltage-based implementations, the communication service provider is faced with the problem that such low voltage restrictions may not provide sufficient voltage headroom to accommodate a low impedance-interface with existing SLICs (which may be designed to operate at a VCC supply rail of five volts).
This limited voltage headroom problem may be illustrated by considering a conventional current mirror architecture, shown in
FIG. 1
, as may be employed in a subscriber line interface circuit, and which is designed to operate with a customary VCC supply rail of five volts. As shown therein, the current mirror comprises an input NPN transistor
10
having its base
11
coupled to a voltage reference V
REF
, and its emitter
12
coupled to receive an emitter current I
12
or input current I
in
, from a communication device, such as a codec, interfaced therewith. The collector
13
of the input NPN transistor
10
is coupled in common to the collector
23
of a first current mirror input PNP transistor
20
, and to the base
31
of a base-offset PNP transistor
30
, the collector
33
of which is coupled to a voltage reference terminal, such as ground (GND). The emitter
32
of PNP transistor
30
is coupled in common to the base
21
of current mirror output transistor
20
and to the base
41
of a PNP current mirror output transistor
40
. The emitters
22
and
42
of current mirror transistors
20
and
40
, respectively, are coupled through resistors
24
and
44
to a (VCC) voltage supply rail
16
, while the collector
43
of the current mirror output transistor
40
is coupled to an output terminal
45
, from which an output current I
out
is derived.
While the current mirror circuit of
FIG. 1
works well when powered by its designed supply rail voltage VCC of five volts, when interfaced with a reduced voltage circuit, such as a differential voltage-based codec operating at a VCC rail value on the order of only three volts and a reference voltage V
REF
of only half that (e.g., on the order of 1.5 to 1.6 volts), the input NPN transistor
10
lacks sufficient overhead for proper circuit operation. Also, even though the mirrored output I
out
at output node
45
is first order compensated for PNP base current errors, it is not compensated for the NPN base current error in input transistor
10
.
More particularly, the mirrored output current I
out
at the current mirror's output terminal
45
corresponds to the collector current I
43
flowing out of the collector
43
of the current mirror transistor
40
, which may be defined as:
 
I
out
=I
43
=&agr;
NPN10
I
12
−2
I
12
/&bgr;
PNP
2
,
or
I
out
=I
12
(&agr;
NPN10
−2/&bgr;
PNP
2
),
so that I
out
may be approximated as:
I
out
=I
in
(1−1/&bgr;
NPN
).  (1)
From equation (1), it can be seen that the mirrored output current I
out
at the collector
43
of current mirror transistor
40
not only includes the input current I
in
, as desired, but it includes a base current error component I
in
/&bgr;
NPN
associated with the NPN input transistor
10
, which is undesired. Because of the extremely tight voltage tolerances associated with the use of the lower VCC supply rail voltage and reference voltage V
REF
, there is no available headroom in the collector-emitter current flow path through transistors 10-20 and the VCC supply rail for the insertion of an NPN base current error compensating circuit.
SUMMARY OF THE INVENTION
In accordance with the present invention, this base current error problem is successfully addressed by means of a compound multiple transistor polarity (PNP and NPN) base current error correction architecture, that is configured around an initial assumption that all transistors of a first polarity transistor type of current mirror output transistor (e.g., PNP for the case of a current mirror employing PNP current mirror output transistors, as a non-limiting example) will be properly compensated for PNP base current errors.
Based upon this initial premise, an NPN base current error compensation mirror circuit, referenced to the collector-emitter current path of an NPN input transistor coupled to a control node used to drive the PNP current mirror transistors, is configured to mirror a first, NPN base current offset to the control node. To compensate for total number of base current error components in the output PNP transistor-based mirror circuit, auxiliary PNP transistors are coupled in the collector-emitter paths of the current mirror PNP transistors and the output current mirror's output ports. Because the output ports are referenced to a relatively large voltage (e.g., V
BAT
), there is sufficient headroom in the collector-emitter paths of the current mirror PNP transistors for the insertion of the auxiliary PNP transistors.
Base offset currents of these auxiliary transistors are summed and mirrored back to the control node by a multiplication factor that is defined in accordance with the base error currents associated with the total mirrored output current produced at the collectors of the current mirror output transistors. As a result, the control node is supplied with a composite (NPN and PNP base error compensated) current mirror control current which, when applied to the output current mirror transistors, causes each of their respective output currents to be effectively equal to the input current (namely, containing no base current error component).


REFERENCES:
patent: 5311146 (1994-05-01), Brannon et al.

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