Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Patent
1993-08-26
1995-07-04
Hjerpe, Richard
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
345 94, 345 98, G09G 336
Patent
active
054304610
ABSTRACT:
A flat panel display has an improved selection circuit for scanning row lines while data signals are applied to column lines for writing a selected image onto the pixel forming elements along the selected row line. The number of row lines, N, is chosen to be the product of two numbers, P and Q and preferably N is a perfect square. A first timing circuit provides Q number of non-overlapping timing signals that each have P narrow clock pulses each of a width for writing data into one row the display; it also provides P number of non-overlapping timing signals that each have clock pulses with a width of Q write operations. For each row line of the display, the selection circuit has an AND logic circuit that responds to one wide pulse clock line and one narrow pulse clock line to connect the row line to a voltage to enable the pixel forming elements to turn on in a write operation. Another logic circuit for each row line selectively connects the line to a voltage to inhibit the turn on of the pixel forming elements. This circuit has a single gate that responds to the complement of the associated narrow pulse clock signal, and this gate closes to isolate a selected line from the inhibiting voltage. The gate is open for only a minimum time so that an unselected line with this gate open can not float electrically to a voltage that could allow its pixel elements to turn on.
REFERENCES:
patent: 4317115 (1982-02-01), Kawakami et al.
patent: 5111195 (1992-05-01), Fukuoka et al.
patent: 5153483 (1992-10-01), Kishino et al.
Chang Vivian
Hjerpe Richard
Industrial Technology Research Institute
Robertson William S.
Saile George O.
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