Transistor arrangement

Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element

Reexamination Certificate

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C324S613000, C365S185240

Reexamination Certificate

active

07598764

ABSTRACT:
A transistor arrangement having a multiplicity of transistors interconnected with one another, having a noise detection device, which is set up for detecting the 1/f noise of at least one portion of the transistors, having a selection device, which is set up for selecting at least one of the transistors, on the basis of the ascertained 1/f noise characteristic of the transistors, in the case of which the 1/f noise is sufficiently low.

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Ralf Brederlow et al.; “Influence of Fluorinated Gate Oxides on the Low Frequency Noise of MOS Transistors under Analog Operation”; In: Proceedings of the 28thEuropean Solid-State Device Research Conference, (1998), pp. 472-475.
Ralf Brederlow et al.; “Fluctuations of the Low Frequency Noise of MOS Transistors and their Modeling in Analog and RF-Circuits”; IEDM 1999 Tech. Dig., pp. 159-162.
S. Christensen et al.; “Low Frequency Noise in MOS Transistors - I Theory”; Solid-State Electronics, 1968, vol. 11, pp. 797-812.

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